Merge remote-tracking branch 'origin/main' into main

efabless · Dec 7, 2021 · 9df0a16 · 9df0a16
2 parents bc05947 + 1db0a08
commit 9df0a16
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Showing 2 changed files with 14 additions and 4 deletions.
diff --git a/verilog/common/includes.gl+sdf.caravel b/verilog/common/includes.gl+sdf.caravel
@@ -20,6 +20,7 @@ $VERILOG_PATH/gl/mgmt_core_wrapper.v
 //$VERILOG_PATH/beh/sky130_sram_2kbyte_1rw1r_32x512_8.v
 
 $PDK_ROOT/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v
+$PDK_ROOT/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v
 $PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
 $PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
 $PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v

diff --git a/verilog/common/includes.gl+sdf.standalone b/verilog/common/includes.gl+sdf.standalone
@@ -9,8 +9,17 @@ $VERILOG_PATH/gl/DFFRAM.v
 $VERILOG_PATH/gl/mgmt_core_wrapper.v
 
 // STD CELLS - they need to be below the defines.v files 
-$VERILOG_PATH/cvc-pdk/sky130_fd_io.v
-$VERILOG_PATH/cvc-pdk/primitives_hd.v
-$VERILOG_PATH/cvc-pdk/sky130_fd_sc_hd.v
-$VERILOG_PATH/beh/sky130_sram_2kbyte_1rw1r_32x512_8.v
+//$VERILOG_PATH/cvc-pdk/sky130_fd_io.v
+//$VERILOG_PATH/cvc-pdk/primitives_hd.v
+//$VERILOG_PATH/cvc-pdk/sky130_fd_sc_hd.v
+//$VERILOG_PATH/cvc-pdk/primitives_hvl.v
+//$VERILOG_PATH/cvc-pdk/sky130_fd_sc_hvl.v
+//$VERILOG_PATH/beh/sky130_sram_2kbyte_1rw1r_32x512_8.v
 
+$PDK_ROOT/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v
+$PDK_ROOT/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v
+$PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
+$PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
+$PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v
+$PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v
+$PDK_ROOT/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v