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Merge pull request #504 from efabless/cocotb
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update cocotb top rtl to work with cheetah soc
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jeffdi authored Oct 23, 2023
2 parents 78a85b1 + 6b58291 commit eab35f8
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Showing 2 changed files with 7 additions and 28 deletions.
2 changes: 1 addition & 1 deletion manifest
Original file line number Diff line number Diff line change
Expand Up @@ -52,7 +52,7 @@ e0c6ead5e35c1ba01d923c482e953c2af9691524 verilog/rtl/mprj_io_buffer.v
669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v
739ca5ed63a513d2e4c9bf3ecfad32d9fa527518 verilog/rtl/simple_por.v
b9d6114a5067a04dd59cdd46fb988591c16743ce verilog/rtl/spare_logic_block.v
036dc8e9066082b2e133dc7b72fd3ad5a52f254b verilog/rtl/toplevel_cocotb.v
9178c87e3d5196fd3e6abae6fc310e1b663ade0e verilog/rtl/toplevel_cocotb.v
8f0bec01c914efe790a09ffe62bbfe0781069e35 verilog/rtl/xres_buf.v
256190717faa72005cf7656d8443c4c0693b3f78 scripts/set_user_id.py
731116709a44d13225170acc83cd34ff9e00fa39 scripts/generate_fill.py
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33 changes: 6 additions & 27 deletions verilog/rtl/toplevel_cocotb.v
Original file line number Diff line number Diff line change
@@ -1,31 +1,6 @@
`timescale 1 ns / 1 ps
`include "includes.v" // in case of RTL coverage is needed and it doesn't work correctly without include files by this way
`ifdef VCS
`ifdef sky130
`ifndef ENABLE_SDF
`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
`else
`include "cvc-pdk/sky130_ef_io.v"
`include "cvc-pdk/sky130_fd_io.v"
`include "cvc-pdk/primitives_hd.v"
`include "cvc-pdk/sky130_fd_sc_hd.v"
`include "cvc-pdk/primitives_hvl.v"
`include "cvc-pdk/sky130_fd_sc_hvl.v"
`endif // ~ ENABLE_SDF
`elsif gf180 // sky180
`include "libs.ref/gf180mcu_fd_io/verilog/gf180mcu_fd_io.v"
// `include "libs.ref/gf180mcu_fd_sc_mcu7t5v0/verilog/GF018hv5v_mcu_sc7_udp.v"
`include "libs.ref/gf180mcu_fd_sc_mcu7t5v0/verilog/primitives.v"
`include "libs.ref/gf180mcu_fd_sc_mcu7t5v0/verilog/gf180mcu_fd_sc_mcu7t5v0.v"
// `include "libs.ref/gf180mcu_sc7_hv/verilog/GF018hv5v_mcu_sc7.v"
`include "libs.ref/gf180mcu_fd_ip_sram/verilog/gf180mcu_fd_ip_sram__sram512x8m8wm1.v"
`endif //sky180
`endif //VCS


module caravel_top ;

Expand All @@ -39,10 +14,12 @@ initial begin
`else
$vcdplusfile("waves.vpd");
`endif
// $vcdplusmemorydump();
$vcdpluson();
`else
$dumpfile ({"waves.vcd"});
$dumpvars (0, caravel_top);

`endif
end
`endif // WAVE_GEN
Expand Down Expand Up @@ -216,7 +193,9 @@ caravel uut (

`endif // ! openframe


`ifdef USE_USER_VIP
`USER_VIP
`endif // USE_USER_VIP

// make speical variables for the mprj input to assign the input without writing to the output gpios
// cocotb limitation #2587: iverilog deal with array as 1 object not multiple of objects so can't write to only 1 element
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