Merge pull request #476 from efabless/remove_depency_over_power

Fix power guards
efabless · Oct 23, 2023 · 4996d33 · 4996d33
2 parents d42e78e + 610a874
commit 4996d33
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Showing 6 changed files with 41 additions and 26 deletions.
diff --git a/manifest b/manifest
@@ -20,9 +20,9 @@ fa26aa34b4b382aacad9b7ac07a36b17172a401f  verilog/rtl/caravel.v
 1bbaa93405d4cb51429eacea4da40014231b11ed  verilog/rtl/caravel_motto.v
 ae07f0d87e69f4dd2026ed841e3a962facac847b  verilog/rtl/caravel_openframe.v
 d97cb60c8d125d6098111d4f0aa00410515770eb  verilog/rtl/caravel_power_routing.v
-bc1e961e41d1d3a383a018279a08bf4108911f53  verilog/rtl/chip_io.v
-f2242e1f295ee5efeacea51698f706a2cfd97c28  verilog/rtl/chip_io_alt.v
-f97affcdbf268c61ada91eed6a2238e52e1b9889  verilog/rtl/chip_io_openframe.v
+e54c181033aa019f0edcaed5ffc71e54c3888970  verilog/rtl/chip_io.v
+1088531d6a69d82b976d4aca7ae923423680a715  verilog/rtl/chip_io_alt.v
+e293e138c6e6f5df76db78bdaa34a35003f6ba5f  verilog/rtl/chip_io_openframe.v
 126aff02aa229dc346301c552d785dec76a4d68e  verilog/rtl/clock_div.v
 941bd7636e7558b045faa3d8c6ba2d91b4c4b798  verilog/rtl/constant_block.v
 58fd210a64e502fb231d843eada4052f923d788d  verilog/rtl/copyright_block.v
@@ -47,10 +47,10 @@ c96ba94e5779ea6afe452d89632eaada73e26aab  verilog/rtl/mprj_io.v
 e0c6ead5e35c1ba01d923c482e953c2af9691524  verilog/rtl/mprj_io_buffer.v
 3baffde4788f01e2ff0e5cd83020a76bd63ef7d7  verilog/rtl/mprj_logic_high.v
 5287821a0ed1994850a978ef0cd024fac51fb6e8  verilog/rtl/open_source.v
-189532aff9e5e2ebbd99befd05cbf50e948b14af  verilog/rtl/openframe_netlists.v
-4edbfd0ad80b69a799a399ffc717b560fcae615b  verilog/rtl/pads.v
+33c8fc54298e5425875aaab8c139074ec7d0e9e9  verilog/rtl/openframe_netlists.v
+b53c154e6acaf44e858c936c8027d0229608676e  verilog/rtl/pads.v
 669d16642d5dd5f6824812754db20db98c9fe17b  verilog/rtl/ring_osc2x13.v
-739ca5ed63a513d2e4c9bf3ecfad32d9fa527518  verilog/rtl/simple_por.v
+83937790b8f5dbcdd7e9a804b5e9bdf475c0ab7d  verilog/rtl/simple_por.v
 b9d6114a5067a04dd59cdd46fb988591c16743ce  verilog/rtl/spare_logic_block.v
 9178c87e3d5196fd3e6abae6fc310e1b663ade0e  verilog/rtl/toplevel_cocotb.v
 8f0bec01c914efe790a09ffe62bbfe0781069e35  verilog/rtl/xres_buf.v

diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
@@ -276,8 +276,10 @@ module chip_io(
     wire [6:0] vssd_const_zero;	// Constant value for management pins
 
     constant_block constant_value_inst [6:0] (
-	.vccd(vccd),
-	.vssd(vssd),
+	`ifdef USE_POWER_PINS
+		.vccd(vccd),
+		.vssd(vssd),
+	`endif // USE_POWER_PINS
 	.one(vccd_const_one),
 	.zero(vssd_const_zero)
     );

diff --git a/verilog/rtl/chip_io_alt.v b/verilog/rtl/chip_io_alt.v
@@ -345,10 +345,12 @@ module chip_io_alt #(
 	wire [6:0] vssd_const_zero; // Constant value for management pins
 
 	constant_block constant_value_inst [6:0] (
-            .vccd(vccd),
-            .vssd(vssd),
-            .one(vccd_const_one),
-            .zero(vssd_const_zero)
+		`ifdef USE_POWER_PINS
+			.vccd(vccd),
+			.vssd(vssd),
+		`endif // USE_POWER_PINS
+		.one(vccd_const_one),
+		.zero(vssd_const_zero)
 	);
 
 	// Management clock input pad

diff --git a/verilog/rtl/chip_io_openframe.v b/verilog/rtl/chip_io_openframe.v
@@ -262,8 +262,10 @@ module chip_io_openframe #(
 	// These are exported to the user project for direct loopback if needed.
 
 	constant_block constant_value_inst [`OPENFRAME_IO_PADS-1:0] (
-		.vccd(vccd),
-		.vssd(vssd),
+		`ifdef USE_POWER_PINS
+			.vccd(vccd),
+			.vssd(vssd),
+		`endif // USE_POWER_PINS
 		.one(gpio_loopback_one),
 		.zero(gpio_loopback_zero)
 	);
@@ -275,8 +277,10 @@ module chip_io_openframe #(
 	wire xres_loopback_zero;
 
 	constant_block constant_value_xres_inst (
-		.vccd(vccd),
-		.vssd(vssd),
+		`ifdef USE_POWER_PINS
+			.vccd(vccd),
+			.vssd(vssd),
+		`endif // USE_POWER_PINS
 		.one(xres_loopback_one),
 		.zero(xres_loopback_zero)	// (unused)
 	);

diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v
@@ -17,7 +17,7 @@
 `ifndef TOP_ROUTING 
 	`define USER1_ABUTMENT_PINS \
 	.AMUXBUS_A(analog_a),\
-	.AMUXBUS_B(analog_b),\
+	.AMUXBUS_B(analog_b),`ifdef USE_POWER_PINS\
 	.VSSA(vssa1),\
 	.VDDA(vdda1),\
 	.VSWITCH(vddio),\
@@ -27,11 +27,11 @@
 	.VCCD(vccd),\
 	.VSSIO(vssio),\
 	.VSSD(vssd),\
-	.VSSIO_Q(vssio_q),
+	.VSSIO_Q(vssio_q),`endif
 
 	`define USER2_ABUTMENT_PINS \
 	.AMUXBUS_A(analog_a),\
-	.AMUXBUS_B(analog_b),\
+	.AMUXBUS_B(analog_b),`ifdef USE_POWER_PINS\
 	.VSSA(vssa2),\
 	.VDDA(vdda2),\
 	.VSWITCH(vddio),\
@@ -41,11 +41,11 @@
 	.VCCD(vccd),\
 	.VSSIO(vssio),\
 	.VSSD(vssd),\
-	.VSSIO_Q(vssio_q),
+	.VSSIO_Q(vssio_q),`endif
 
 	`define MGMT_ABUTMENT_PINS \
 	.AMUXBUS_A(analog_a),\
-	.AMUXBUS_B(analog_b),\
+	.AMUXBUS_B(analog_b), `ifdef USE_POWER_PINS \
 	.VSSA(vssa),\
 	.VDDA(vdda),\
 	.VSWITCH(vddio),\
@@ -55,7 +55,7 @@
 	.VCCD(vccd),\
 	.VSSIO(vssio),\
 	.VSSD(vssd),\
-	.VSSIO_Q(vssio_q),
+	.VSSIO_Q(vssio_q), `endif
 `else 
 	`define USER1_ABUTMENT_PINS 
 	`define USER2_ABUTMENT_PINS 

diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v
@@ -44,12 +44,19 @@ module simple_por(
     // down.  Note that this is sped way up for verilog simulation;  the
     // actual circuit is set to a 15ms delay.
 
-    always @(posedge vdd3v3) begin
+    `ifdef USE_POWER_PINS
+        always @(posedge vdd3v3) begin
+    `else
+        initial begin
+    `endif
 	#500 inode <= 1'b1;
     end
-    always @(negedge vdd3v3) begin
-	#500 inode <= 1'b0;
-    end
+
+    `ifdef USE_POWER_PINS
+        always @(negedge vdd3v3) begin
+        #500 inode <= 1'b0;
+        end
+    `endif
 
     // Instantiate two shmitt trigger buffers in series