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This PR adds the guide for VPL on Moodle, VPL scripts and files for the VPL test 1.
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# Moodle VPL | ||
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1. Din cadrul cursului vom selecta "SIMULARE VPL" | ||
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![VPL1](../media/VPL1.png) | ||
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2. Veți avea următoarea fereastră care va conține descrierea exercițiului și fișierele pe care le puteți modifica. Pentru a le edita apăsați butonul "EDIT". | ||
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![VPL2](../media/VPL2.png) | ||
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3. În cadrul IDE-ului VPL veți avea un tab cu fiecare fișier (mux.v, test_mux.v), punctajul în dreapta, rezultatele compilării sau evaluării. | ||
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![VPL3](../media/VPL3.png) | ||
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4. Puteți modifica fișierul "mux.v". Atât timp cât fișierele nu sunt salvate veți avea o stea în dreptul numelui fișierului. Pentru a salva apăsați butonul "Save". | ||
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![VPL4](../media/VPL4.png) | ||
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5. O dată salvat fișierul steaua va dispărea. Acum puteți apăsa pe butonul "Run" pentru a vedea enunțul. | ||
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![VPL5](../media/VPL5.png) | ||
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6. Se va porni o consolă ca în imaginea următoare. Veți avea detalii despre implementarea pe care o aveți de făcut și rezultatele rulării modului nostru de test/simulare. | ||
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![VPL6](../media/VPL6.png) | ||
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7. Pentru a evalua soluția voastră puteți apăsa butonul "Evaluate". Nota va fi modificată în dreapta și vom avea descrierea implementării și primul test eșuat. | ||
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![VPL7](../media/VPL7.png) | ||
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8. Pentru a vedea mai bine detaliile testului puteți modifica mărimea ferestrelor. | ||
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![VPL8](../media/VPL8.png) | ||
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9. Daca doriți să rulați testele voastre pentru a face debug, puteți modifica fișierul "test_mux.v". | ||
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![VPL9](../media/VPL9.png) | ||
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10. Folosim butonul "Run" și vom vedea rezultatele simulării. | ||
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![VPL10](../media/VPL10.png) |
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*.vvp | ||
*.vcd | ||
vpl_execution |
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COMPILER=iverilog | ||
INTERPRETER=vvp | ||
SIMULATOR=gtkwave | ||
FLAGS=-Wall -Winfloop | ||
SOLUTION_FLAGS=-DDIGIT1=1 -DDIGIT2=2 -DDIGIT3=3 -DDIGIT4=4 | ||
TOP_MODULE=alu | ||
TOP_SIM_MODULE=test_${TOP_MODULE} | ||
TOP_EVALUATE_MODULE=evaluate_${TOP_MODULE} | ||
SOLUTION_MODULE=sol | ||
SOLUTION_SIM_MODULE=test_${SOLUTION_MODULE} | ||
OTHER_SOURCES=bigalu.v | ||
DUMP_VCD_FILE=test.vcd | ||
EVALUATE_FILE=evaluate.out | ||
GRADE_SCRIPT=grade.sh | ||
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all: build | ||
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build: | ||
$(COMPILER) $(FLAGS) $(TOP_MODULE).v $(TOP_SIM_MODULE).v $(OTHER_SOURCES) -o $(TOP_MODULE).vvp | ||
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build_solution: | ||
$(COMPILER) $(FLAGS) ${SOLUTION_FLAGS} ${SOLUTION_SIM_MODULE}.v ${SOLUTION_MODULE}.v $(OTHER_SOURCES) -o $(SOLUTION_MODULE).vvp | ||
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build_evaluate: | ||
$(COMPILER) $(FLAGS) ${SOLUTION_FLAGS} ${TOP_MODULE}.v ${SOLUTION_MODULE}.v ${TOP_EVALUATE_MODULE}.v $(OTHER_SOURCES) -o $(TOP_EVALUATE_MODULE).vvp | ||
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run: build | ||
$(INTERPRETER) $(TOP_MODULE).vvp | ||
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run_solution: build_solution | ||
$(INTERPRETER) $(SOLUTION_MODULE).vvp | ||
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run_evaluate: build_evaluate | ||
$(INTERPRETER) $(TOP_EVALUATE_MODULE).vvp > $(EVALUATE_FILE) 2>&1 | ||
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simulate: run | ||
$(SIMULATOR) $(DUMP_VCD_FILE) | ||
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simulate_solution: run_solution | ||
$(SIMULATOR) $(DUMP_VCD_FILE) | ||
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evaluate: run_evaluate | ||
./${GRADE_SCRIPT} $(EVALUATE_FILE) | ||
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clean: | ||
rm *.vvp $(DUMP_VCD_FILE) $(EVALUATE_FILE) |
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Implmentați modulul verilog pentru un ALU (arithmetic logic unit) cu 2 operanzi i_w_op1 și i_w_op2 pe 4 biți fiecare, cu rezultatul pe 4 biți o_w_out și o linie de selecție pe 2 biți a operație i_w_sel. | ||
Apăsați butonul run din VPL pentru a afla operațile pe care trebuie sa le implementați pentru fiecare selecție. |
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module alu( | ||
output wire [3:0] o_w_out, | ||
input wire [3:0] i_w_op1, | ||
input wire [3:0] i_w_op2, | ||
input wire [1:0 ] i_w_sel | ||
); | ||
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//TODO: Implement the digital logic for the 7-segment display | ||
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endmodule |
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module bigalu( | ||
output wire [3:0] o_w_out, | ||
input wire [3:0] i_w_op1, | ||
input wire [3:0] i_w_op2, | ||
input wire [3:0 ] i_w_sel | ||
); | ||
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reg [3:0] l_r_out; | ||
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always @(*) begin | ||
case(i_w_sel) | ||
4'b0000: l_r_out = i_w_op1 + i_w_op2; // add | ||
4'b0001: l_r_out = i_w_op1 - i_w_op2; // sub | ||
4'b0010: l_r_out = i_w_op1 & i_w_op2; // and | ||
4'b0011: l_r_out = i_w_op1 | i_w_op2; // or | ||
4'b0100: l_r_out = i_w_op1 ^ i_w_op2; // xor | ||
4'b0101: l_r_out = i_w_op1 << i_w_op2; // shift left | ||
4'b0110: l_r_out = i_w_op1 >> i_w_op2; // shift right | ||
4'b0111: l_r_out = i_w_op1 >>> i_w_op2; // shift right arithmetic | ||
4'b1000: l_r_out = i_w_op1 * i_w_op2; // multiply | ||
4'b1001: l_r_out = i_w_op1 / i_w_op2; // divide | ||
4'b1010: l_r_out = i_w_op1 % i_w_op2; // modulo | ||
4'b1011: l_r_out = i_w_op1 == i_w_op2; // equal | ||
4'b1100: l_r_out = i_w_op1 < i_w_op2; // less than | ||
4'b1101: l_r_out = i_w_op1 > i_w_op2; // greater than | ||
4'b1110: l_r_out = ~(i_w_op1 & i_w_op2); // NAND | ||
4'b1111: l_r_out = ~(i_w_op1 | i_w_op2); // NOR | ||
endcase | ||
end | ||
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assign o_w_out = l_r_out; | ||
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endmodule |
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`timescale 1ns / 1ps | ||
module evaluate_alu; | ||
//Inputs | ||
reg[3:0] l_r_op1; | ||
reg[3:0] l_r_op2; | ||
reg[1:0] l_r_sel; | ||
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//Outputs | ||
wire[3:0] l_w_out; | ||
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//Expected outputs | ||
wire[3:0] l_w_sout; | ||
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//local variables for loop | ||
integer i, j, k; | ||
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//Module initialization | ||
alu uut ( | ||
.o_w_out(l_w_out), | ||
.i_w_op1(l_r_op1), | ||
.i_w_op2(l_r_op2), | ||
.i_w_sel(l_r_sel) | ||
); | ||
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//Expected module initialization | ||
sol l_m_sol ( | ||
.o_w_out(l_w_sout), | ||
.i_w_op1(l_r_op1), | ||
.i_w_op2(l_r_op2), | ||
.i_w_sel(l_r_sel) | ||
); | ||
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//Simulation tests | ||
initial begin | ||
for(i=0;i<4;i=i+1) begin | ||
l_r_sel = i; | ||
for(j=0;j<16;j=j+1) begin | ||
l_r_op1 = j; | ||
for(k=0;k<16;k=k+1) begin | ||
l_r_op2 = k; | ||
#5; | ||
if (l_w_out !== l_w_sout) begin | ||
$display("Error: (hex_values) l_w_out = %0h correct %0h, op1 = %0h, op2 = %0h, sel = %0h", l_w_out, l_w_sout, l_r_op1, l_r_op2, l_r_sel); | ||
end else begin | ||
$display("OK"); | ||
end | ||
#5; | ||
end | ||
end | ||
end | ||
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//finish the simulation | ||
$finish; | ||
end | ||
endmodule |
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#!/bin/bash | ||
if [[ $# -ne 1 ]]; then | ||
echo 'Too many/few arguments, expecting one' >&2 | ||
exit 1 | ||
fi | ||
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EVALUATE_FILE=$1 | ||
#--- remove multiple spaces --- | ||
cat $EVALUATE_FILE | sed 's/ */ /g' > dummy.out | ||
mv dummy.out $EVALUATE_FILE | ||
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#--- remove blank lines --- | ||
cat $EVALUATE_FILE | sed '/^\s*$/d' > dummy.out | ||
mv dummy.out $EVALUATE_FILE | ||
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# Calculate number of correct test versus wrong test | ||
correct_test_no=$(awk '$1=="OK" { print $0 }' $EVALUATE_FILE | wc -l | awk '{ print $1 }') | ||
test_no=$(wc -l $EVALUATE_FILE| awk '{ print $1 }') | ||
grade=$( expr $correct_test_no \* 100 / $test_no) | ||
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echo $grade |
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module sol( | ||
output wire [3:0] o_w_out, | ||
input wire [3:0] i_w_op1, | ||
input wire [3:0] i_w_op2, | ||
input wire [1:0 ] i_w_sel | ||
); | ||
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reg [3:0] l_r_sop0; | ||
reg [3:0] l_r_sop1; | ||
reg [3:0] l_r_sop2; | ||
reg [3:0] l_r_sop3; | ||
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wire [3:0] l_w_res0_out; | ||
wire [3:0] l_w_res1_out; | ||
wire [3:0] l_w_res2_out; | ||
wire [3:0] l_w_res3_out; | ||
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initial begin | ||
l_r_sop0 <= 4'd`OP0; | ||
l_r_sop1 <= 4'd`OP1; | ||
l_r_sop2 <= 4'd`OP2; | ||
l_r_sop3 <= 4'd`OP3; | ||
end | ||
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bigalu l_m_res0( | ||
.o_w_out(l_w_res0_out), | ||
.i_w_op1(i_w_op1), | ||
.i_w_op2(i_w_op2), | ||
.i_w_sel(l_r_sop0) | ||
); | ||
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bigalu l_m_res1( | ||
.o_w_out(l_w_res1_out), | ||
.i_w_op1(i_w_op1), | ||
.i_w_op2(i_w_op2), | ||
.i_w_sel(l_r_sop1) | ||
); | ||
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bigalu l_m_res2( | ||
.o_w_out(l_w_res2_out), | ||
.i_w_op1(i_w_op1), | ||
.i_w_op2(i_w_op2), | ||
.i_w_sel(l_r_sop2) | ||
); | ||
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bigalu l_m_res3( | ||
.o_w_out(l_w_res3_out), | ||
.i_w_op1(i_w_op1), | ||
.i_w_op2(i_w_op2), | ||
.i_w_sel(l_r_sop3) | ||
); | ||
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assign o_w_out = (i_w_sel == 2'b00) ? l_w_res0_out : | ||
(i_w_sel == 2'b01) ? l_w_res1_out : | ||
(i_w_sel == 2'b10) ? l_w_res2_out : | ||
l_w_res3_out; | ||
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endmodule |
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`timescale 1ns / 1ps | ||
module test_alu; | ||
//Inputs | ||
reg[3:0] l_r_op1; | ||
reg[3:0] l_r_op2; | ||
reg[1:0] l_r_sel; | ||
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//Outputs | ||
wire[3:0] l_w_out; | ||
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//local variables for loop | ||
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//Module initialization | ||
alu uut ( | ||
.o_w_out(l_w_out), | ||
.i_w_op1(l_r_op1), | ||
.i_w_op2(l_r_op2), | ||
.i_w_sel(l_r_sel) | ||
); | ||
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//Simulation tests | ||
initial begin | ||
// monitor varibles changes in values | ||
$monitor( | ||
"Time = %0t, ", $time, | ||
"l_w_out = %0h, ", l_w_out, | ||
"l_r_op1 = %0h, ", l_r_op1, | ||
"l_r_op2 = %0h, ", l_r_op2, | ||
"l_r_sel = %0h, ", l_r_sel | ||
); | ||
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l_r_op1 = 4'b0010; | ||
l_r_op2 = 4'b0100; | ||
l_r_sel = 2'b00; | ||
#10; | ||
l_r_sel = 2'b01; | ||
#10; | ||
l_r_sel = 2'b10; | ||
#10; | ||
l_r_sel = 2'b11; | ||
#10; | ||
//finish the simulation | ||
$finish; | ||
end | ||
endmodule |
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