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Full RV32I support, except for fence, ebreak, csrr
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@ckirsch
ckirsch committed Jan 10, 2024
1 parent c514b72 commit 1e9e86b
Showing 1 changed file with 86 additions and 14 deletions.
100 changes: 86 additions & 14 deletions tools/rotor.c
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Original file line number Diff line number Diff line change
Expand Up @@ -841,7 +841,10 @@ uint64_t* decode_imm(uint64_t* sid, uint64_t* ir_nid,
uint64_t* slli_nid, uint64_t* srli_nid, uint64_t* srai_nid, char* comment,
uint64_t* no_funct3_nid, uint64_t* no_funct7_nid, uint64_t* other_opcode_nid);
uint64_t* decode_op(uint64_t* sid, uint64_t* ir_nid,
uint64_t* add_nid, uint64_t* sub_nid, uint64_t* sltu_nid,
uint64_t* add_nid, uint64_t* sub_nid,
uint64_t* slt_nid, uint64_t* sltu_nid,
uint64_t* xor_nid, uint64_t* or_nid, uint64_t* and_nid,
uint64_t* sll_nid, uint64_t* srl_nid, uint64_t* sra_nid,
uint64_t* mul_nid, uint64_t* divu_nid, uint64_t* remu_nid, char* comment,
uint64_t* no_funct3_nid, uint64_t* no_funct7_nid, uint64_t* other_opcode_nid);
uint64_t* decode_load(uint64_t* sid, uint64_t* ir_nid,
Expand Down Expand Up @@ -1045,7 +1048,7 @@ uint64_t* NID_F3_SRA = (uint64_t*) 0;
uint64_t* NID_F3_OR = (uint64_t*) 0;
uint64_t* NID_F3_AND = (uint64_t*) 0;

uint64_t* NID_F7_SLL_SRL_ADD_SLT_XOR_OR_AND = (uint64_t*) 0;
uint64_t* NID_F7_ADD_SLT_XOR_OR_AND_SLL_SRL = (uint64_t*) 0;
uint64_t* NID_F7_SUB_SRA = (uint64_t*) 0;

uint64_t* NID_F7_SLL_SRL_ILLEGAL = (uint64_t*) 0;
Expand Down Expand Up @@ -1283,7 +1286,7 @@ void init_instruction_sorts() {
NID_F3_OR = new_constant(OP_CONST, SID_FUNCT3, F3_OR, 3, "F3_OR");
NID_F3_AND = new_constant(OP_CONST, SID_FUNCT3, F3_AND, 3, "F3_AND");

NID_F7_SLL_SRL_ADD_SLT_XOR_OR_AND = NID_F7_ADD;
NID_F7_ADD_SLT_XOR_OR_AND_SLL_SRL = NID_F7_ADD;
NID_F7_SUB_SRA = NID_F7_SUB;

NID_F7_SLL_SRL_ILLEGAL = new_constant(OP_CONST, SID_FUNCT7, F7_ADD + 1, 7, "F7_SLL_SRL_ILLEGAL");
Expand Down Expand Up @@ -3047,7 +3050,7 @@ uint64_t* decode_illegal_shift_imm(uint64_t* sid, uint64_t* ir_nid,
NID_F3_SRL, "illegal SRLI?",
srli_nid, format_comment("illegal srli %s", (uint64_t) comment),
no_funct3_nid)),
format_comment("illegal SLLI or SRLI %s", (uint64_t) comment),
format_comment("illegal slli or srli %s", (uint64_t) comment),
decode_funct7(sid, ir_nid,
NID_F7_SRA_ILLEGAL, "illegal SRAI?",
decode_funct3(sid, ir_nid,
Expand Down Expand Up @@ -3086,15 +3089,15 @@ uint64_t* decode_imm(uint64_t* sid, uint64_t* ir_nid,
NID_F3_AND, "ANDI?",
andi_nid, format_comment("andi %s", (uint64_t) comment),
decode_funct7(sid, ir_nid,
NID_F7_SLL_SRL_ADD_SLT_XOR_OR_AND, "SLLI or SRLI?",
NID_F7_ADD_SLT_XOR_OR_AND_SLL_SRL, "SLLI or SRLI?",
decode_funct3(sid, ir_nid,
NID_F3_SLL, "SLLI?",
slli_nid, format_comment("slli %s", (uint64_t) comment),
decode_funct3(sid, ir_nid,
NID_F3_SRL, "SRLI?",
srli_nid, format_comment("srli %s", (uint64_t) comment),
no_funct3_nid)),
format_comment("SLLI or SRLI %s", (uint64_t) comment),
format_comment("slli or srli %s", (uint64_t) comment),
decode_funct7(sid, ir_nid,
NID_F7_SUB_SRA, "SRAI?",
decode_funct3(sid, ir_nid,
Expand All @@ -3108,28 +3111,52 @@ uint64_t* decode_imm(uint64_t* sid, uint64_t* ir_nid,
}

uint64_t* decode_op(uint64_t* sid, uint64_t* ir_nid,
uint64_t* add_nid, uint64_t* sub_nid, uint64_t* sltu_nid,
uint64_t* add_nid, uint64_t* sub_nid,
uint64_t* slt_nid, uint64_t* sltu_nid,
uint64_t* xor_nid, uint64_t* or_nid, uint64_t* and_nid,
uint64_t* sll_nid, uint64_t* srl_nid, uint64_t* sra_nid,
uint64_t* mul_nid, uint64_t* divu_nid, uint64_t* remu_nid, char* comment,
uint64_t* no_funct3_nid, uint64_t* no_funct7_nid, uint64_t* other_opcode_nid) {
return decode_opcode(sid, ir_nid,
NID_OP_OP, "OP?",
decode_funct7(sid, ir_nid,
NID_F7_SLL_SRL_ADD_SLT_XOR_OR_AND, "ADD or SLTU?",
NID_F7_ADD_SLT_XOR_OR_AND_SLL_SRL, "ADD or SLTU?",
decode_funct3(sid, ir_nid,
NID_F3_ADD_SUB_MUL, "ADD?",
add_nid, format_comment("add %s", (uint64_t) comment),
decode_funct3(sid, ir_nid,
NID_F3_SLTU, "SLTU?",
sltu_nid, format_comment("sltu %s", (uint64_t) comment),
no_funct3_nid)),
format_comment("add or sltu %s", (uint64_t) comment),
NID_F3_SLT, "SLT?",
slt_nid, format_comment("slt %s", (uint64_t) comment),
decode_funct3(sid, ir_nid,
NID_F3_SLTU, "SLTU?",
sltu_nid, format_comment("sltu %s", (uint64_t) comment),
decode_funct3(sid, ir_nid,
NID_F3_XOR, "XOR?",
xor_nid, format_comment("xor %s", (uint64_t) comment),
decode_funct3(sid, ir_nid,
NID_F3_OR, "OR?",
or_nid, format_comment("or %s", (uint64_t) comment),
decode_funct3(sid, ir_nid,
NID_F3_AND, "AND?",
and_nid, format_comment("and %s", (uint64_t) comment),
decode_funct3(sid, ir_nid,
NID_F3_SLL, "SLL?",
sll_nid, format_comment("sll %s", (uint64_t) comment),
decode_funct3(sid, ir_nid,
NID_F3_SRL, "SRL?",
srl_nid, format_comment("srl %s", (uint64_t) comment),
no_funct3_nid)))))))),
format_comment("add or slt or sltu or xor or or or and or sll or srl %s", (uint64_t) comment),
decode_funct7(sid, ir_nid,
NID_F7_SUB_SRA, "SUB?",
decode_funct3(sid, ir_nid,
NID_F3_ADD_SUB_MUL, "SUB?",
sub_nid, format_comment("sub %s", (uint64_t) comment),
no_funct3_nid),
format_comment("sub %s", (uint64_t) comment),
decode_funct3(sid, ir_nid,
NID_F3_SRA, "SRA?",
sra_nid, format_comment("sra %s", (uint64_t) comment),
no_funct3_nid)),
format_comment("sub or sra %s", (uint64_t) comment),
decode_funct7(sid, ir_nid,
NID_F7_MUL_DIV_REM, "MUL or DIVU or REMU?",
decode_funct3(sid, ir_nid,
Expand Down Expand Up @@ -3276,7 +3303,14 @@ uint64_t* decode_instruction(uint64_t* ir_nid) {
decode_op(SID_BOOLEAN, ir_nid,
NID_ADD,
NID_SUB,
NID_SLT,
NID_SLTU,
NID_XOR,
NID_OR,
NID_AND,
NID_SLL,
NID_SRL,
NID_SRA,
NID_MUL,
NID_DIVU,
NID_REMU,
Expand Down Expand Up @@ -3385,13 +3419,44 @@ uint64_t* op_data_flow(uint64_t* ir_nid, uint64_t* other_data_flow_nid) {
rs1_value_nid,
rs2_value_nid,
"rs1 value - rs2 value"),
new_ext(OP_UEXT, SID_MACHINE_WORD,
new_binary_boolean(OP_SLT,
rs1_value_nid,
rs2_value_nid,
"rs1 value < rs2 value?"),
WORDSIZEINBITS - 1,
"unsigned-extend Boolean to machine word"),
new_ext(OP_UEXT, SID_MACHINE_WORD,
new_binary_boolean(OP_ULT,
rs1_value_nid,
rs2_value_nid,
"rs1 value < rs2 value (unsigned)?"),
WORDSIZEINBITS - 1,
"unsigned-extend Boolean to machine word"),
new_binary(OP_XOR, SID_MACHINE_WORD,
rs1_value_nid,
rs2_value_nid,
"rs1 value ^ rs2 value"),
new_binary(OP_OR, SID_MACHINE_WORD,
rs1_value_nid,
rs2_value_nid,
"rs1 value | rs2 value"),
new_binary(OP_AND, SID_MACHINE_WORD,
rs1_value_nid,
rs2_value_nid,
"rs1 value & rs2 value"),
new_binary(OP_SLL, SID_MACHINE_WORD,
rs1_value_nid,
rs2_value_nid,
"rs1 value << rs2 value"),
new_binary(OP_SRL, SID_MACHINE_WORD,
rs1_value_nid,
rs2_value_nid,
"rs1 value >> rs2 value"),
new_binary(OP_SRA, SID_MACHINE_WORD,
rs1_value_nid,
rs2_value_nid,
"signed rs1 value >> rs2 value"),
new_binary(OP_MUL, SID_MACHINE_WORD,
rs1_value_nid,
rs2_value_nid,
Expand Down Expand Up @@ -4174,6 +4239,13 @@ void rotor() {
UNUSED,
new_binary_boolean(OP_AND,
decode_op(SID_BOOLEAN, ir_nid,
NID_FALSE,
NID_FALSE,
NID_FALSE,
NID_FALSE,
NID_FALSE,
NID_FALSE,
NID_FALSE,
NID_FALSE,
NID_FALSE,
NID_FALSE,
Expand Down

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