add missing memory fences for tppc32le and pb variants

c/atomic.h

@@ -34,6 +34,10 @@
 # define STORE_FENCE() __asm__ __volatile__ ("dbar 0" : : : "memory")
 # define ACQUIRE_FENCE() __asm__ __volatile__ ("dbar 0" : : : "memory")
 # define RELEASE_FENCE() __asm__ __volatile__ ("dbar 0" : : : "memory")
+#elif (__GNUC__ >= 5) || defined(__clang__)
+# define STORE_FENCE() __sync_synchronize()
+# define ACQUIRE_FENCE() STORE_FENCE()
+# define RELEASE_FENCE() STORE_FENCE()
 #else
 # define STORE_FENCE() do { } while (0)
 #endif
@@ -150,9 +154,9 @@ FORCEINLINE int S_cas_any_fence(volatile void *addr, void *old_val, void *new_va
 }
 # define CAS_ANY_FENCE(a, old, new) S_cas_any_fence(a, old, new)
 #elif defined(__riscv)
-# error expected a compiler with a CS intrinsic for RISC-V
+# error expected a compiler with a CAS intrinsic for RISC-V
 #elif defined(__loongarch64)
-# error TODO
+# error expected a compiler with a CAS intrinsic for LoongArch64
 #else
 # define CAS_ANY_FENCE(a, old, new) ((*(ptr *)(a) == TO_PTR(old)) ? (*(ptr *)(a) = TO_PTR(new), 1) : 0)
 #endif

release_notes/release_notes.stex

@@ -2726,6 +2726,13 @@ in fasl files does not generally make sense.
 %-----------------------------------------------------------------------------
 \section{Bug Fixes}\label{section:bugfixes}
 
+\subsection{Missing memory fences for some platforms (10.1.0)}
+
+Compilation for tppc32le lacked memory fences that are needed to
+ensure safety on multicore machines. The pb machine variant also
+needed a more portable approach to memory fences via compiler
+intrinsics (as needed for MIPS, for example).
+
 \subsection{Bounds checking and collection for some reference-bytevector lengths (10.1.0)}
 
 When a reference bytevector's length is smaller than the machine's

s/cpprim.ss

@@ -631,7 +631,7 @@
     (define need-store-fence?
       (if-feature pthreads
 	              (constant-case architecture
-                                 [(arm32 arm64 riscv64 loongarch64 pb) #t]
+                                 [(arm32 arm64 riscv64 loongarch64 ppc32 pb) #t]
                                  [else #f])
                   #f))
     (define add-store-fence

s/ppc32.ss

@@ -701,6 +701,18 @@
                `(set! ,(make-live-info) ,u (asm ,null-info ,asm-kill))
                `(asm ,info ,asm-cas ,base ,index ,old ,new ,u)))))]))
 
+  (define-instruction effect (store-store-fence)
+    [(op)
+     `(asm ,info ,(asm-fence 'store-store))])
+
+  (define-instruction effect (acquire-fence)
+    [(op)
+     `(asm ,info ,(asm-fence 'acquire))])
+
+  (define-instruction effect (release-fence)
+    [(op)
+     `(asm ,info ,(asm-fence 'release))])
+
   (define-instruction effect (pause)
     [(op) `(asm ,info ,asm-isync)])
 
@@ -744,7 +756,7 @@
                      asm-direct-jump asm-return-address asm-jump asm-conditional-jump
                      asm-indirect-call asm-condition-code
                      asm-trunc asm-fpt asm-fpcastto asm-fpcastfrom asm-fpsingle
-                     asm-lock asm-lock+/- asm-cas
+                     asm-lock asm-lock+/- asm-cas asm-fence
                      asm-load-single->double asm-store-double->single
                      asm-fpop-2 asm-c-simple-call
                      asm-save-flrv asm-restore-flrv asm-return asm-c-return asm-size
@@ -971,6 +983,7 @@
   (define-op mtxer move-to-special-reg-op (ax-spr-code 'xer))
 
   (define-op isync isync-op)
+  (define-op sync  sync-op)
 
   (define arithmetic-op
     (lambda (op opcode set-cr? set-oe? dest-ea opnd0-ea opnd1-ea code*)
@@ -1237,6 +1250,16 @@
         [1  #b0010010110]
         [0  #b0])))
 
+  (define sync-op
+    (lambda (op code*)
+      (emit-code (op code*)
+        [26 #b011111]
+        [21 #b00000]
+        [16 #b00000]
+        [11 #b00000]
+        [1  #b1001010110]
+        [0  #b0])))
+
   (define-syntax emit-code
     (lambda (x)
       ; NB: probably won't need emit-code to weed out #f
@@ -1773,6 +1796,11 @@
               (emit stwcx. new base index
                 code*)))))))
 
+  (define-who asm-fence
+    (lambda (kind)
+      (lambda (code*)
+        (emit sync code*))))
+
   (define asm-fp-relop
     (lambda (info)
       (lambda (l1 l2 offset x y)