[major] Move Extmodule Params to Instantiation

spec.md

@@ -217,12 +217,9 @@ instance statement for details on how to instantiate a module
 ## Externally Defined Modules
 
 Externally defined modules are modules whose implementation is not provided in
-the current circuit. Only the ports and name of the externally defined module
-are specified in the circuit. An externally defined module may include, in
-order, an optional _defname_ which sets the name of the external module in the
-resulting Verilog and zero or more name--value _parameter_ statements. Each
-name--value parameter statement will result in a value being passed to the named
-parameter in the resulting Verilog.
+the current circuit. Only the ports of the externally defined module are
+specified in the circuit. No other statements may exist in the external module
+body.
 
 An example of an externally defined module is:
 
@@ -231,15 +228,36 @@ extmodule MyExternalModule :
  input foo: UInt<2>
  output bar: UInt<4>
  output baz: SInt<8>
- defname = VerilogName
- parameter x = "hello"
- parameter y = 42
 ```
 
 The widths of all externally defined module ports must be specified. Width
 inference, described in [@sec:width-inference], is not supported for module
 ports.
 
+Externally defined modules may have zero or more parameters. Parameters may be
+of known-width `UInt`{.firrtl} or `SInt`{.firrtl} types or `String`{.firrtl}
+type. The value of a parameter is set at each instantiation of an external
+module using a literal value.
+
+An example of a parametric externally defined module and its instantiation is:
+
+``` firrtl
+extmodule MyExternalModule2<
+ parameter x: String,
+ parameter y: UInt<8>,
+ parameter z: SInt<4>
+> :
+ ; ...
+module Top:
+ inst foo of MyExternalModule2<"hello", UInt<8>(42), SInt<4>(-1)>
+ inst bar of MyExternalModule2<"world", UInt(0), SInt(-2)>
+```
+
+As shown above, it is allowable to use a smaller, unknown width integer type
+literal to set a parameter value so long as the width of the underlying
+parameter value is large enough to store the literal type. A literal that is
+too large for a given parameter type is illegal.
+
 A common use of an externally defined module is to represent a Verilog module
 that will be written separately and provided together with FIRRTL-generated
 Verilog to downstream tools.
@@ -2899,8 +2917,8 @@ primop_1expr2int =
 primop = primop_2expr | primop_1expr | primop_1expr1int | primop_1expr2int ;
 
 (* Expression definitions *)
-expr =
- ( "UInt" | "SInt" ) , [ width ] , "(" , ( int ) , ")"
+int_lit = ( "UInt" | "SInt" ) , [ width ] , "(" , int , ")"
+expr = int_lit
  | reference
  | "mux" , "(" , expr , "," , expr , "," , expr , ")"
  | "validif" , "(" , expr , "," , expr , ")"
@@ -2924,11 +2942,13 @@ memory = "mem" , id , ":" , [ info ] , newline , indent ,
  dedent ;
 
 (* Statements *)
+parameter = int_lit | string ;
+parameter_seq = parameter | parameter , "," , parameter_seq ;
 statement = "wire" , id , ":" , type , [ info ]
  | "reg" , id , ":" , type , expr ,
  [ "(with: {reset => (" , expr , "," , expr ")})" ] , [ info ]
  | memory
- | "inst" , id , "of" , id , [ info ]
+ | "inst" , id , "of" , id , [ "<" , parameter_seq , ">" ] , [ info ]
  | "node" , id , "=" , expr , [ info ]
  | reference , "<=" , expr , [ info ]
  | reference , "<-" , expr , [ info ]
@@ -2948,10 +2968,11 @@ module = "module" , id , ":" , [ info ] , newline , indent ,
  { port , newline } ,
  { statement , newline } ,
  dedent ;
-extmodule = "extmodule" , id , ":" , [ info ] , newline , indent ,
+parameter_decl = "parameter" , id , ":" , type ;
+parameter_decl_seq = parameter_decl | parameter_decl , "," , parameter_decl_seq ;
+extmodule = "extmodule" , id , [ "<" , parameter_decl_seq , ">" ] , ":" ,
+ [ info ] , newline , indent ,
  { port , newline } ,
- [ "defname" , "=" , id , newline ] ,
- { "parameter" , "=" , ( string | int ) , newline } ,
  dedent ;
 
 (* Version definition *)