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Signed-off-by: Unai Martinez-Corral <[email protected]>
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# Clock pin | ||
set_property PACKAGE_PIN E3 [get_ports {clk}] | ||
set_property IOSTANDARD LVCMOS33 [get_ports {clk}] | ||
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# LEDs | ||
set_property PACKAGE_PIN H5 [get_ports {led[0]}] | ||
set_property PACKAGE_PIN J5 [get_ports {led[1]}] | ||
set_property PACKAGE_PIN T9 [get_ports {led[2]}] | ||
set_property PACKAGE_PIN T10 [get_ports {led[3]}] | ||
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] | ||
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] | ||
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] | ||
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] | ||
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# Clock constraints | ||
create_clock -period 10.0 [get_ports {clk}] |
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{ | ||
"default_part": "XC7A35TCSG324-1", | ||
"values": { | ||
"top": "top" | ||
}, | ||
"dependencies": { | ||
"sources": [ | ||
"counter.v" | ||
], | ||
"synth_log": "synth.log", | ||
"pack_log": "pack.log" | ||
}, | ||
"XC7A35TCSG324-1": { | ||
"default_target": "bitstream", | ||
"dependencies": { | ||
"build_dir": "build/arty_35", | ||
"xdc": [ | ||
"arty.xdc" | ||
] | ||
}, | ||
"values": { | ||
"part": "xc7a35tcpg236-1" | ||
} | ||
} | ||
} |
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module top ( | ||
input clk, | ||
output [3:0] led | ||
); | ||
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localparam BITS = 4; | ||
localparam LOG2DELAY = 22; | ||
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wire bufg; | ||
BUFG bufgctrl ( | ||
.I(clk), | ||
.O(bufg) | ||
); | ||
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reg [BITS+LOG2DELAY-1:0] counter = 0; | ||
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always @(posedge bufg) begin | ||
counter <= counter + 1; | ||
end | ||
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assign led[3:0] = counter >> LOG2DELAY; | ||
endmodule |
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top.v |
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synth: | ||
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docker run --rm \ | ||
-v /$(shell pwd)://wrk -w //wrk \ | ||
gcr.io/hdl-containers/ghdl \ | ||
ghdl synth --std=08 --out=verilog counter.vhd -e Arty_Counter > top.v | ||
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synth-plugin: | ||
docker run --rm \ | ||
-v /$(shell pwd)://wrk -w //wrk \ | ||
gcr.io/hdl-containers/ghdl/yosys \ | ||
yosys -m ghdl -p 'ghdl --std=08 counter.vhd -e Arty_Counter; write_verilog top.v' |
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# Clock pin | ||
set_property PACKAGE_PIN E3 [get_ports {CLK}] | ||
set_property IOSTANDARD LVCMOS33 [get_ports {CLK}] | ||
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||
# LEDs | ||
set_property PACKAGE_PIN H5 [get_ports {LEDs[0]}] | ||
set_property PACKAGE_PIN J5 [get_ports {LEDs[1]}] | ||
set_property PACKAGE_PIN T9 [get_ports {LEDs[2]}] | ||
set_property PACKAGE_PIN T10 [get_ports {LEDs[3]}] | ||
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs[0]}] | ||
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs[1]}] | ||
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs[2]}] | ||
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs[3]}] | ||
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||
# Clock constraints | ||
create_clock -period 10.0 [get_ports {CLK}] |
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{ | ||
"default_part": "XC7A35TCSG324-1", | ||
"values": { | ||
"top": "top" | ||
}, | ||
"dependencies": { | ||
"sources": [ | ||
"top.v" | ||
], | ||
"synth_log": "synth.log", | ||
"pack_log": "pack.log" | ||
}, | ||
"XC7A35TCSG324-1": { | ||
"default_target": "bitstream", | ||
"dependencies": { | ||
"build_dir": "build/arty_35", | ||
"xdc": [ | ||
"arty.xdc" | ||
] | ||
}, | ||
"values": { | ||
"part": "xc7a35tcpg236-1" | ||
} | ||
} | ||
} |
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library ieee; | ||
context ieee.ieee_std_context; | ||
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entity Arty_Counter is | ||
port ( | ||
CLK : in std_logic; | ||
LEDs : out std_logic_vector(3 downto 0) | ||
); | ||
end; | ||
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architecture arch of Arty_Counter is | ||
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constant LOG2DELAY : natural := 22; | ||
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signal counter : unsigned(LEDs'length+LOG2DELAY-1 downto 0) := (others=>'0'); | ||
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begin | ||
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process (CLK) begin | ||
counter <= counter + 1 when rising_edge(CLK); | ||
end process; | ||
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LEDs <= std_logic_vector(resize(shift_right(counter, LOG2DELAY), LEDs'length)); | ||
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end; |