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add HDL tests
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Signed-off-by: Unai Martinez-Corral <[email protected]>
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umarcor committed Aug 29, 2022
1 parent d430b6c commit 655600c
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75 changes: 75 additions & 0 deletions .github/workflows/Action.yml
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Expand Up @@ -137,3 +137,78 @@ jobs:
name: Action-SymbiFlow-eos-s3-Bitstream
path: f4pga-examples/eos-s3/btn_counter/build/top.bit
if-no-files-found: error


Test-Verilog:
runs-on: ubuntu-latest

steps:

- name: 🧰 Checkout
uses: actions/checkout@v3

- name: 🚧 F4PGA Action (arty_35 | verilog/counter)
uses: ./action
with:
image: xc7/a50t
cmd: |
cd test/verilog/counter
f4pga build --flow arty_35.json
- name: '📤 Upload artifact: Arty 35 bitstream'
uses: actions/upload-artifact@v3
with:
name: arty_35-Bitstream-Verilog-Counter
path: test/verilog/counter/top.bit


Test-VHDL:
runs-on: ubuntu-latest

steps:

- name: 🧰 Checkout
uses: actions/checkout@v3

- name: 🚧 GHDL synth
run: make -C test/vhdl/counter synth

- name: 🚧 F4PGA Action (arty_35 | vhdl/counter)
uses: ./action
with:
image: xc7/a50t
cmd: |
cd test/vhdl/counter
f4pga build --flow arty_35.json
- name: '📤 Upload artifact: Arty 35 bitstream'
uses: actions/upload-artifact@v3
with:
name: arty_35-Bitstream-VHDL-Counter
path: test/vhdl/counter/top.bit


Test-VHDL-plugin:
runs-on: ubuntu-latest

steps:

- name: 🧰 Checkout
uses: actions/checkout@v3

- name: 🚧 GHDL synth
run: make -C test/vhdl/counter synth-plugin

- name: 🚧 F4PGA Action (arty_35 | vhdl/counter)
uses: ./action
with:
image: xc7/a50t
cmd: |
cd test/vhdl/counter
f4pga build --flow arty_35.json
- name: '📤 Upload artifact: Arty 35 bitstream'
uses: actions/upload-artifact@v3
with:
name: arty_35-Bitstream-VHDL-plugin-Counter
path: test/vhdl/counter/top.bit
16 changes: 16 additions & 0 deletions test/verilog/counter/arty.xdc
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# Clock pin
set_property PACKAGE_PIN E3 [get_ports {clk}]
set_property IOSTANDARD LVCMOS33 [get_ports {clk}]

# LEDs
set_property PACKAGE_PIN H5 [get_ports {led[0]}]
set_property PACKAGE_PIN J5 [get_ports {led[1]}]
set_property PACKAGE_PIN T9 [get_ports {led[2]}]
set_property PACKAGE_PIN T10 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]

# Clock constraints
create_clock -period 10.0 [get_ports {clk}]
25 changes: 25 additions & 0 deletions test/verilog/counter/arty_35.json
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{
"default_part": "XC7A35TCSG324-1",
"values": {
"top": "top"
},
"dependencies": {
"sources": [
"counter.v"
],
"synth_log": "synth.log",
"pack_log": "pack.log"
},
"XC7A35TCSG324-1": {
"default_target": "bitstream",
"dependencies": {
"build_dir": "build/arty_35",
"xdc": [
"arty.xdc"
]
},
"values": {
"part": "xc7a35tcpg236-1"
}
}
}
22 changes: 22 additions & 0 deletions test/verilog/counter/counter.v
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module top (
input clk,
output [3:0] led
);

localparam BITS = 4;
localparam LOG2DELAY = 22;

wire bufg;
BUFG bufgctrl (
.I(clk),
.O(bufg)
);

reg [BITS+LOG2DELAY-1:0] counter = 0;

always @(posedge bufg) begin
counter <= counter + 1;
end

assign led[3:0] = counter >> LOG2DELAY;
endmodule
1 change: 1 addition & 0 deletions test/vhdl/counter/.gitignore
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top.v
12 changes: 12 additions & 0 deletions test/vhdl/counter/Makefile
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synth:

docker run --rm \
-v /$(shell pwd)://wrk -w //wrk \
gcr.io/hdl-containers/ghdl \
ghdl synth --std=08 --out=verilog counter.vhd -e Arty_Counter > top.v

synth-plugin:
docker run --rm \
-v /$(shell pwd)://wrk -w //wrk \
gcr.io/hdl-containers/ghdl/yosys \
yosys -m ghdl -p 'ghdl --std=08 counter.vhd -e Arty_Counter; write_verilog top.v'
16 changes: 16 additions & 0 deletions test/vhdl/counter/arty.xdc
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# Clock pin
set_property PACKAGE_PIN E3 [get_ports {CLK}]
set_property IOSTANDARD LVCMOS33 [get_ports {CLK}]

# LEDs
set_property PACKAGE_PIN H5 [get_ports {LEDs[0]}]
set_property PACKAGE_PIN J5 [get_ports {LEDs[1]}]
set_property PACKAGE_PIN T9 [get_ports {LEDs[2]}]
set_property PACKAGE_PIN T10 [get_ports {LEDs[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LEDs[3]}]

# Clock constraints
create_clock -period 10.0 [get_ports {CLK}]
25 changes: 25 additions & 0 deletions test/vhdl/counter/arty_35.json
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{
"default_part": "XC7A35TCSG324-1",
"values": {
"top": "top"
},
"dependencies": {
"sources": [
"top.v"
],
"synth_log": "synth.log",
"pack_log": "pack.log"
},
"XC7A35TCSG324-1": {
"default_target": "bitstream",
"dependencies": {
"build_dir": "build/arty_35",
"xdc": [
"arty.xdc"
]
},
"values": {
"part": "xc7a35tcpg236-1"
}
}
}
25 changes: 25 additions & 0 deletions test/vhdl/counter/counter.vhd
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library ieee;
context ieee.ieee_std_context;

entity Arty_Counter is
port (
CLK : in std_logic;
LEDs : out std_logic_vector(3 downto 0)
);
end;

architecture arch of Arty_Counter is

constant LOG2DELAY : natural := 22;

signal counter : unsigned(LEDs'length+LOG2DELAY-1 downto 0) := (others=>'0');

begin

process (CLK) begin
counter <= counter + 1 when rising_edge(CLK);
end process;

LEDs <= std_logic_vector(resize(shift_right(counter, LOG2DELAY), LEDs'length));

end;

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