add HDL tests

Signed-off-by: Unai Martinez-Corral <[email protected]>

.github/workflows/Action.yml

@@ -137,3 +137,81 @@ jobs:
  name: Action-SymbiFlow-eos-s3-Bitstream
  path: f4pga-examples/eos-s3/btn_counter/build/top.bit
  if-no-files-found: error
+
+
+ Test-Verilog:
+ runs-on: ubuntu-latest
+ name: 🎬 Verilog
+
+ steps:
+
+ - name: 🧰 Checkout
+ uses: actions/checkout@v3
+
+ - name: 🚧 F4PGA Action (arty_35 | verilog/counter)
+ uses: ./action
+ with:
+ image: xc7/a50t
+ cmd: |
+ cd test/verilog/counter
+ f4pga build --flow arty_35.json
+
+ - name: '📤 Upload artifact: Arty 35 bitstream'
+ uses: actions/upload-artifact@v3
+ with:
+ name: arty_35-Bitstream-Verilog-Counter
+ path: test/verilog/counter/top.bit
+
+
+ Test-VHDL:
+ runs-on: ubuntu-latest
+ name: 🎬 VHDL
+
+ steps:
+
+ - name: 🧰 Checkout
+ uses: actions/checkout@v3
+
+ - name: 🚧 GHDL synth
+ run: make -C test/vhdl/counter synth
+
+ - name: 🚧 F4PGA Action (arty_35 | vhdl/counter)
+ uses: ./action
+ with:
+ image: xc7/a50t
+ cmd: |
+ cd test/vhdl/counter
+ f4pga build --flow arty_35.json
+
+ - name: '📤 Upload artifact: Arty 35 bitstream'
+ uses: actions/upload-artifact@v3
+ with:
+ name: arty_35-Bitstream-VHDL-Counter
+ path: test/vhdl/counter/top.bit
+
+
+ Test-VHDL-plugin:
+ runs-on: ubuntu-latest
+ name: 🎬 VHDL-plugin
+
+ steps:
+
+ - name: 🧰 Checkout
+ uses: actions/checkout@v3
+
+ - name: 🚧 GHDL synth
+ run: make -C test/vhdl/counter synth-plugin
+
+ - name: 🚧 F4PGA Action (arty_35 | vhdl/counter)
+ uses: ./action
+ with:
+ image: xc7/a50t
+ cmd: |
+ cd test/vhdl/counter
+ f4pga build --flow arty_35.json
+
+ - name: '📤 Upload artifact: Arty 35 bitstream'
+ uses: actions/upload-artifact@v3
+ with:
+ name: arty_35-Bitstream-VHDL-plugin-Counter
+ path: test/vhdl/counter/top.bit

test/constraints/arty.xdc

@@ -0,0 +1,32 @@
+# Copyright (C) 2020-2022 F4PGA Authors.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Clock pin
+set_property PACKAGE_PIN E3 [get_ports {CLK}]
+set_property IOSTANDARD LVCMOS33 [get_ports {CLK}]
+
+# LEDs
+set_property PACKAGE_PIN H5 [get_ports {LEDs[0]}]
+set_property PACKAGE_PIN J5 [get_ports {LEDs[1]}]
+set_property PACKAGE_PIN T9 [get_ports {LEDs[2]}]
+set_property PACKAGE_PIN T10 [get_ports {LEDs[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LEDs[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LEDs[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LEDs[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LEDs[3]}]
+
+# Clock constraints
+create_clock -period 10.0 [get_ports {CLK}]

test/verilog/counter/arty_35.json

@@ -0,0 +1,25 @@
+{
+ "default_part": "XC7A35TCSG324-1",
+ "values": {
+ "top": "top"
+ },
+ "dependencies": {
+ "sources": [
+ "counter.v"
+ ],
+ "synth_log": "synth.log",
+ "pack_log": "pack.log"
+ },
+ "XC7A35TCSG324-1": {
+ "default_target": "bitstream",
+ "dependencies": {
+ "build_dir": "build/arty_35",
+ "xdc": [
+ "../../constraints/arty.xdc"
+ ]
+ },
+ "values": {
+ "part": "xc7a35tcpg236-1"
+ }
+ }
+}

test/verilog/counter/counter.v

@@ -0,0 +1,40 @@
+/*
+* Copyright (C) 2020-2022 F4PGA Authors.
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* https://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+* SPDX-License-Identifier: Apache-2.0
+*/
+
+module top (
+ input CLK,
+ output [3:0] LEDs
+);
+
+ localparam BITS = 4;
+ localparam LOG2DELAY = 22;
+
+ wire bufg;
+ BUFG bufgctrl (
+ .I(CLK),
+ .O(bufg)
+ );
+
+ reg [BITS+LOG2DELAY-1:0] counter = 0;
+
+ always @(posedge bufg) begin
+ counter <= counter + 1;
+ end
+
+ assign LEDs[3:0] = counter >> LOG2DELAY;
+endmodule

test/vhdl/counter/.gitignore

@@ -0,0 +1 @@
+top.v

test/vhdl/counter/Makefile

@@ -0,0 +1,27 @@
+# Copyright (C) 2020-2022 F4PGA Authors.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+synth:
+ docker run --rm \
+ -v /$(shell pwd)://wrk -w //wrk \
+ gcr.io/hdl-containers/ghdl \
+ ghdl synth --std=08 --out=verilog counter.vhd -e Arty_Counter > Arty_Counter.v
+
+synth-plugin:
+ docker run --rm \
+ -v /$(shell pwd)://wrk -w //wrk \
+ gcr.io/hdl-containers/ghdl/yosys \
+ yosys -m ghdl -p 'ghdl --std=08 counter.vhd -e Arty_Counter; write_verilog Arty_Counter.v'

test/vhdl/counter/arty_35.json

@@ -0,0 +1,25 @@
+{
+ "default_part": "XC7A35TCSG324-1",
+ "values": {
+ "top": "Arty_Counter"
+ },
+ "dependencies": {
+ "sources": [
+ "Arty_Counter.v"
+ ],
+ "synth_log": "synth.log",
+ "pack_log": "pack.log"
+ },
+ "XC7A35TCSG324-1": {
+ "default_target": "bitstream",
+ "dependencies": {
+ "build_dir": "build/arty_35",
+ "xdc": [
+ "../../constraints/arty.xdc"
+ ]
+ },
+ "values": {
+ "part": "xc7a35tcpg236-1"
+ }
+ }
+}

test/vhdl/counter/counter.vhd

@@ -0,0 +1,41 @@
+-- Copyright (C) 2020-2022 F4PGA Authors.
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- https://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- SPDX-License-Identifier: Apache-2.0
+
+library ieee;
+context ieee.ieee_std_context;
+
+entity Arty_Counter is
+ port (
+ CLK : in std_logic;
+ LEDs : out std_logic_vector(3 downto 0)
+ );
+end;
+
+architecture arch of Arty_Counter is
+
+ constant LOG2DELAY : natural := 22;
+
+ signal counter : unsigned(LEDs'length+LOG2DELAY-1 downto 0) := (others=>'0');
+
+begin
+
+ process (CLK) begin
+ counter <= counter + 1 when rising_edge(CLK);
+ end process;
+
+ LEDs <= std_logic_vector(resize(shift_right(counter, LOG2DELAY), LEDs'length));
+
+end;