rpc: add support for wiring.Component.

Do not infer the ports from the publicly accessible wires, but instead
delegate finding the ports to the `rtlil.convert` function.

.github/workflows/main.yaml

@@ -62,11 +62,11 @@ jobs:
  strategy:
  fail-fast: false
  matrix:
- project:
- - amaranth-lang/amaranth-boards
- - amaranth-lang/amaranth-stdio
- - amaranth-lang/amaranth-soc
- name: 'smoke (${{ matrix.project }})'
+ project: # test the last commit before dropping py3.8
+ - { name: amaranth-lang/amaranth-boards, ref: 19b97324ecf9111c5d16377af79f82aad761c476 }
+ - { name: amaranth-lang/amaranth-stdio, ref: 2da45b8e75421879d1096495a4fb438de705f567 }
+ - { name: amaranth-lang/amaranth-soc, ref: 746709e1e992bccf6e2362450243cafd00d72a14 }
+ name: 'smoke (${{ matrix.project.name }})'
  steps:
  - name: Check out Amaranth source code
  uses: actions/checkout@v4
@@ -76,7 +76,8 @@ jobs:
  - name: Check out source code
  uses: actions/checkout@v4
  with:
- repository: ${{ matrix.project }}
+ repository: ${{ matrix.project.name }}
+ ref: ${{ matrix.project.ref }}
  path: project
  fetch-depth: 0
  - name: Set up PDM

amaranth/rpc.py

@@ -3,6 +3,8 @@
 import argparse
 import importlib
 
+from amaranth.lib.wiring import Signature
+
 from .hdl import Signal, Record, Elaboratable
 from .back import rtlil
 
@@ -68,12 +70,14 @@ def _serve_yosys(modules):
 
  try:
  elaboratable = modules[module_name](*args, **kwargs)
- ports = []
- # By convention, any public attribute that is a Signal or a Record is
- # considered a port.
- for port_name, port in vars(elaboratable).items():
- if not port_name.startswith("_") and isinstance(port, (Signal, Record)):
- ports += port._lhs_signals()
+ ports = None
+ if not (hasattr(elaboratable, "signature") and isinstance(elaboratable.signature, Signature)):
+ ports = []
+ # By convention, any public attribute that is a Signal or a Record is
+ # considered a port.
+ for port_name, port in vars(elaboratable).items():
+ if not port_name.startswith("_") and isinstance(port, (Signal, Record)):
+ ports += port._lhs_signals()
  rtlil_text = rtlil.convert(elaboratable, name=module_name, ports=ports)
  response = {"frontend": "ilang", "source": rtlil_text}
  except Exception as error:

docs/changes.rst

@@ -9,6 +9,7 @@ Documentation for past releases
 
 Documentation for past releases of the Amaranth language and toolchain is available online:
 
+* `Amaranth 0.5.3 <https://amaranth-lang.org/docs/amaranth/v0.5.3/>`_
 * `Amaranth 0.5.2 <https://amaranth-lang.org/docs/amaranth/v0.5.2/>`_
 * `Amaranth 0.5.1 <https://amaranth-lang.org/docs/amaranth/v0.5.1/>`_
 * `Amaranth 0.5.0 <https://amaranth-lang.org/docs/amaranth/v0.5.0/>`_
@@ -21,8 +22,8 @@ Documentation for past releases of the Amaranth language and toolchain is availa
 * `Amaranth 0.3 <https://amaranth-lang.org/docs/amaranth/v0.3/>`_
 
 
-Version 0.5.3 (unreleased)
-==========================
+Version 0.5.3
+=============
 
 
 Language changes
@@ -31,6 +32,12 @@ Language changes
 * Added: individual bits of the same signal can now be assigned from different modules or domains.
 
 
+Toolchain changes
+-----------------
+
+* Added: the Amaranth RPC server can now elaborate :class:`amaranth.lib.wiring.Component` objects on demand.
+
+
 Version 0.5.2
 =============
 

pyproject.toml

@@ -81,7 +81,8 @@ docs = [
  "sphinx-autobuild",
 ]
 examples = [
- "amaranth-boards @ git+https://github.com/amaranth-lang/amaranth-boards.git"
+ # pin to last commit with py3.8 support
+ "amaranth-boards @ git+https://github.com/amaranth-lang/amaranth-boards.git@19b97324ecf9111c5d16377af79f82aad761c476"
 ]
 
 [tool.pdm.scripts]