Remove use of deprecated log2_int function.

See amaranth-lang/rfcs#17.

amaranth_soc/csr/bus.py

@@ -2,7 +2,7 @@
 from amaranth import *
 from amaranth.lib import enum, wiring
 from amaranth.lib.wiring import In, Out, flipped
-from amaranth.utils import log2_int
+from amaranth.utils import ceil_log2
 
 from ..memory import MemoryMap
 
@@ -384,13 +384,13 @@ def add(self, elem_range):
  Arguments
  ---------
  elem_range : :class:`range`
- Address range of a CSR :class:`Element`. It uses ``2 ** ceil(log2(elem_range.stop -
- elem_range.start))`` chunks of the shadow register. If this amount is greater than
+ Address range of a CSR :class:`Element`. It uses ``2 ** ceil_log2(elem_range.stop -
+ elem_range.start)`` chunks of the shadow register. If this amount is greater than
  :attr:`~Multiplexer._Shadow.size`, it replaces the latter.
  """
  assert isinstance(elem_range, range)
  self._ranges.add(elem_range)
- elem_size = 2 ** log2_int(elem_range.stop - elem_range.start, need_pow2=False)
+ elem_size = 2 ** ceil_log2(elem_range.stop - elem_range.start)
  self._size = max(self._size, elem_size)
 
  def decode_address(self, addr, elem_range):
@@ -415,7 +415,7 @@ def decode_address(self, addr, elem_range):
  |0001|11|00|
  +----+--+--+
  │ └─ 0
- └──── ceil(log2(elem_range.stop - elem_range.start))
+ └──── ceil_log2(elem_range.stop - elem_range.start)
 
  The upper bits of the offset would be ``0b10``, extracted from ``elem_range.start``:
 
@@ -425,13 +425,13 @@ def decode_address(self, addr, elem_range):
  |0001|10|11|
  +----+--+--+
  │ │
- │ └──── ceil(log2(elem_range.stop - elem_range.start))
+ │ └──── ceil_log2(elem_range.stop - elem_range.start)
  └─────── log2(self.size)
 
  The decoded offset would therefore be ``8`` (i.e. ``0b1000``).
  """
  assert elem_range in self._ranges and addr in elem_range
- elem_size = 2 ** log2_int(elem_range.stop - elem_range.start, need_pow2=False)
+ elem_size = 2 ** ceil_log2(elem_range.stop - elem_range.start)
  self_mask = self.size - 1
  elem_mask = elem_size - 1
  return elem_range.start & self_mask & ~elem_mask | addr & elem_mask
@@ -446,7 +446,7 @@ def encode_offset(self, offset, elem_range):
  located at ``offset``. See :meth:`~Multiplexer._Shadow.decode_address` for details.
  """
  assert elem_range in self._ranges and isinstance(offset, int)
- elem_size = 2 ** log2_int(elem_range.stop - elem_range.start, need_pow2=False)
+ elem_size = 2 ** ceil_log2(elem_range.stop - elem_range.start)
  return elem_range.start + ((offset - elem_range.start) % elem_size)
 
  def prepare(self):

amaranth_soc/csr/event.py

@@ -4,7 +4,7 @@
 from amaranth import *
 from amaranth.lib import wiring
 from amaranth.lib.wiring import In, Out, flipped, connect
-from amaranth.utils import log2_int
+from amaranth.utils import ceil_log2
 
 from . import Element, Multiplexer
 from .. import event
@@ -58,7 +58,7 @@ def __init__(self, event_map, *, trigger="level", data_width, alignment=0, name=
  self._pending = Element(event_map.size, "rw")
 
  elem_size = ceil(event_map.size / data_width)
- addr_width = 1 + max(log2_int(elem_size, need_pow2=False), alignment)
+ addr_width = 1 + max(ceil_log2(elem_size), alignment)
  self._mux = Multiplexer(addr_width=addr_width, data_width=data_width,
  alignment=alignment)
  self._mux.add(self._enable, name="enable")

amaranth_soc/csr/wishbone.py

@@ -1,7 +1,7 @@
 from amaranth import *
 from amaranth.lib import wiring
 from amaranth.lib.wiring import In, flipped
-from amaranth.utils import log2_int
+from amaranth.utils import exact_log2
 
 from . import Interface
 from .. import wishbone
@@ -51,9 +51,10 @@ def __init__(self, csr_bus, *, data_width=None, name=None):
  if data_width is None:
  data_width = csr_bus.data_width
 
- wb_sig = wishbone.Signature(addr_width=max(0, csr_bus.addr_width -
- log2_int(data_width // csr_bus.data_width)),
- data_width=data_width, granularity=csr_bus.data_width)
+ ratio = data_width // csr_bus.data_width
+ wb_sig = wishbone.Signature(addr_width=max(0, csr_bus.addr_width - exact_log2(ratio)),
+ data_width=data_width,
+ granularity=csr_bus.data_width)
 
  super().__init__({"wb_bus": In(wb_sig)})
 
@@ -76,7 +77,7 @@ def elaborate(self, platform):
  m = Module()
 
  cycle = Signal(range(len(wb_bus.sel) + 1))
- m.d.comb += csr_bus.addr.eq(Cat(cycle[:log2_int(len(wb_bus.sel))], wb_bus.adr))
+ m.d.comb += csr_bus.addr.eq(Cat(cycle[:exact_log2(len(wb_bus.sel))], wb_bus.adr))
 
  with m.If(wb_bus.cyc & wb_bus.stb):
  with m.Switch(cycle):

amaranth_soc/wishbone/bus.py

@@ -1,7 +1,7 @@
 from amaranth import *
 from amaranth.lib import enum, wiring
 from amaranth.lib.wiring import In, Out, flipped
-from amaranth.utils import log2_int
+from amaranth.utils import exact_log2
 
 from ..memory import MemoryMap
 
@@ -273,7 +273,7 @@ def memory_map(self, memory_map):
  if memory_map.data_width != self.granularity:
  raise ValueError(f"Memory map has data width {memory_map.data_width}, which is "
  f"not the same as bus interface granularity {self.granularity}")
- granularity_bits = log2_int(self.data_width // self.granularity)
+ granularity_bits = exact_log2(self.data_width // self.granularity)
  effective_addr_width = self.addr_width + granularity_bits
  if memory_map.addr_width != max(1, effective_addr_width):
  raise ValueError(f"Memory map has address width {memory_map.addr_width}, which is "
@@ -318,7 +318,7 @@ def __init__(self, *, addr_width, data_width, granularity=None, features=frozens
  super().__init__({"bus": In(Signature(addr_width=addr_width, data_width=data_width,
  granularity=granularity, features=features))})
  self.bus.memory_map = MemoryMap(
- addr_width=max(1, addr_width + log2_int(data_width // granularity)),
+ addr_width=max(1, addr_width + exact_log2(data_width // granularity)),
  data_width=granularity, alignment=alignment, name=name)
  self._subs = dict()
 
@@ -382,7 +382,7 @@ def elaborate(self, platform):
  sub_bus = self._subs[sub_map]
 
  m.d.comb += [
- sub_bus.adr.eq(self.bus.adr << log2_int(sub_ratio)),
+ sub_bus.adr.eq(self.bus.adr << exact_log2(sub_ratio)),
  sub_bus.dat_w.eq(self.bus.dat_w),
  sub_bus.sel.eq(Cat(sel.replicate(sub_ratio) for sel in self.bus.sel)),
  sub_bus.we.eq(self.bus.we),
@@ -395,7 +395,7 @@ def elaborate(self, platform):
  if hasattr(sub_bus, "bte"):
  m.d.comb += sub_bus.bte.eq(getattr(self.bus, "bte", BurstTypeExt.LINEAR))
 
- granularity_bits = log2_int(self.bus.data_width // self.bus.granularity)
+ granularity_bits = exact_log2(self.bus.data_width // self.bus.granularity)
  with m.Case(sub_pat[:-granularity_bits if granularity_bits > 0 else None]):
  m.d.comb += [
  sub_bus.cyc.eq(self.bus.cyc),