write_verilog: emit initial $display correctly.

backends/verilog/verilog_backend.cc

@@ -1896,17 +1896,21 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 
 void dump_sync_print(std::ostream &f, std::string indent, const RTLIL::SigSpec &trg, const RTLIL::Const &polarity, std::vector<const RTLIL::Cell*> &cells)
 {
- f << stringf("%s" "always @(", indent.c_str());
- for (int i = 0; i < trg.size(); i++) {
- if (i != 0)
- f << " or ";
- if (polarity[i])
- f << "posedge ";
- else
- f << "negedge ";
- dump_sigspec(f, trg[i]);
+ if (trg.size() == 0) {
+ f << stringf("%s" "initial begin\n", indent.c_str());
+ } else {
+ f << stringf("%s" "always @(", indent.c_str());
+ for (int i = 0; i < trg.size(); i++) {
+ if (i != 0)
+ f << " or ";
+ if (polarity[i])
+ f << "posedge ";
+ else
+ f << "negedge ";
+ dump_sigspec(f, trg[i]);
+ }
+ f << ") begin\n";
  }
- f << ") begin\n";
 
  std::sort(cells.begin(), cells.end(), [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
  return a->getParam(ID::PRIORITY).as_int() > b->getParam(ID::PRIORITY).as_int();

docs/source/CHAPTER_CellLib.rst

@@ -120,7 +120,7 @@ All binary RTL cells have two input ports ``\A`` and ``\B`` and one output port
  :verilog:`Y = A >>> B` $sshr :verilog:`Y = A - B` $sub
  :verilog:`Y = A && B` $logic_and :verilog:`Y = A * B` $mul
  :verilog:`Y = A || B` $logic_or :verilog:`Y = A / B` $div
- :verilog:`Y = A === B` $eqx :verilog:`Y = A % B` $mod 
+ :verilog:`Y = A === B` $eqx :verilog:`Y = A % B` $mod
  :verilog:`Y = A !== B` $nex ``N/A`` $divfloor
  :verilog:`Y = A ** B` $pow ``N/A`` $modfoor
  ======================= ============= ======================= =========
@@ -661,6 +661,8 @@ Ports:
 
 ``\TRG``
  The signals that control when this ``$print`` cell is triggered.
+ If the width of this port is zero and ``\TRG_ENABLE`` is true, the cell is
+ triggered during initial evaluation (time zero) only.
 
 ``\EN``
  Enable signal for the whole cell.

frontends/ast/genrtlil.cc

@@ -718,7 +718,7 @@ struct AST_INTERNAL::ProcessGenerator
  }
  }
  cell->parameters[ID::TRG_WIDTH] = triggers.size();
- cell->parameters[ID::TRG_ENABLE] = !triggers.empty();
+ cell->parameters[ID::TRG_ENABLE] = (always->type == AST_INITIAL) || !triggers.empty();
  cell->parameters[ID::TRG_POLARITY] = polarity;
  cell->parameters[ID::PRIORITY] = --last_print_priority;
  cell->setPort(ID::TRG, triggers);