Example involving different but equivalent submodules

examples/simple/.gitignore

@@ -7,3 +7,4 @@
 /ex_amend/
 /fsm/
 /hierarchy/
+/submodules/

examples/simple/Makefile

@@ -1,6 +1,6 @@
 EQY := eqy
 
-test: aliases/PASS combine/PASS counter/PASS ex_amend/PASS ex_bind/PASS ex_group/PASS ex_join/PASS fsm/PASS hierarchy/PASS
+test: aliases/PASS combine/PASS counter/PASS ex_amend/PASS ex_bind/PASS ex_group/PASS ex_join/PASS fsm/PASS hierarchy/PASS submodules/PASS
 
 aliases/PASS: aliases.eqy aliases.sv
 	$(EQY) -f aliases.eqy
@@ -29,7 +29,10 @@ fsm/PASS: fsm.eqy fsm.sv
 hierarchy/PASS: hierarchy.eqy hierarchy.sv
 	$(EQY) -f hierarchy.eqy
 
+submodules/PASS: submodules.eqy submodules.sv
+	$(EQY) -f submodules.eqy
+
 clean:
-	rm -rf aliases/ combine/ counter/ ex_amend/ ex_bind/ ex_group/ ex_join/ fsm/ hierarchy/
+	rm -rf aliases/ combine/ counter/ ex_amend/ ex_bind/ ex_group/ ex_join/ fsm/ hierarchy/ submodules/
 
 .PHONY: test clean

examples/simple/submodules.eqy

@@ -0,0 +1,15 @@
+[gold]
+read_verilog -sv -DGOLD submodules.sv
+[gate]
+read_verilog -sv -DGATE submodules.sv
+
+[script]
+prep -top top
+
+[strategy sat]
+use sat
+depth 5
+
+[strategy pdr]
+use sby
+engine abc pdr -rfi

examples/simple/submodules.sv

@@ -0,0 +1,63 @@
+`ifdef GOLD
+
+
+module submod(input [7:0] a, input [7:0] b, output [7:0] outp);
+    assign outp = a + b;
+endmodule
+
+module top(input clk, input [7:0] a, output [7:0] b);
+
+    reg [15:0] counter = 0;
+
+    always @(posedge clk)
+        counter <= counter + a;
+
+
+    wire [7:0] tmp;
+
+    submod submod(.a(counter[7:0]), .b(counter[15:8]), .outp(tmp));
+
+    reg [7:0] counter2 = 0;
+
+    always @(posedge clk)
+        counter2 <= counter2 + tmp;
+
+    assign b = counter2;
+
+endmodule
+`endif
+
+
+`ifdef GATE
+
+module submod(input [7:0] a, input [7:0] b, output [7:0] outp);
+    assign outp = ((a * 7) + (b * 7)) * 183;
+endmodule
+
+
+module top(input clk, input [7:0] a, output [7:0] b);
+    reg [15:0] counter_late = 0;
+    reg [7:0] a_d = 0;
+
+
+    always @(posedge clk)
+        a_d <= a;
+
+    always @(posedge clk)
+        counter_late <= counter_late + a_d;
+
+    wire [15:0] counter = counter_late + a_d;
+
+    wire [7:0] tmp;
+
+    submod submod(.a(counter[7:0]), .b(counter[15:8]), .outp(tmp));
+
+    reg [7:0] neg_counter2 = 0;
+
+    always @(posedge clk)
+        neg_counter2 <= neg_counter2 - tmp;
+
+    assign b = -neg_counter2;
+endmodule
+
+`endif