Merge branch 'main' into dyn_objFifo_fix

.gitignore

@@ -6,6 +6,7 @@
 /cmakeModules*
 .vscode
 __pycache__
+.ipynb_checkpoints
 .DS_Store
 **/CMakeFiles
 **.cmake
@@ -23,4 +24,4 @@ lib/**/Makefile
 /platforms/vck190_bare/vivado/*.xsa
 /platforms/vck190_bare/vivado/vck190_bare_proj
 utils/vitisVariables.config
-runtime_lib/xaiengine/src
+runtime_lib/xaiengine/src

.pre-commit-config.yaml

@@ -0,0 +1,6 @@
+repos:
+- repo: https://github.com/kynan/nbstripout
+  rev: 0.8.0
+  hooks:
+    - id: nbstripout 
+      args: [--drop-empty-cells]

include/aie/Dialect/AIE/IR/AIEOps.td

@@ -1046,10 +1046,8 @@ def AIE_DMAOp: AIE_Op<"dma", [
   }];
 }
 
-// MemOps are not actually Callable, but we want to inline code into them, so we have to
-// implement CallableOpInterface
 def AIE_MemOp: AIE_Op<"mem", [
-    TileElement, FlowEndPoint, CallableOpInterface,
+    TileElement, FlowEndPoint,
     IsCoreTile, HasValidBDs, HasValidDMAChannels,
     DeclareOpInterfaceMethods<InferTypeOpInterface>
   ]>, Results<(outs Index)> {
@@ -1084,19 +1082,12 @@ def AIE_MemOp: AIE_Op<"mem", [
     int colIndex();
     int rowIndex();
     TileOp getTileOp();
-    int maxSizeInBytes() { return 32768; }
-    // CallableOpInterface
-    mlir::Region *getCallableRegion();
-    llvm::ArrayRef<mlir::Type> getArgumentTypes() { return getOperand().getType(); }
-    llvm::ArrayRef<mlir::Type> getResultTypes() { return getType(); }
     using ::xilinx::AIE::TileElement::Trait<MemOp>::getAsmResultNames;
   }];
 }
 
-// This op is not actually Callable, but we want to inline code into them, so we have to
-// implement CallableOpInterface
 def AIE_MemTileDMAOp: AIE_Op<"memtile_dma", [
-    TileElement, FlowEndPoint, CallableOpInterface,
+    TileElement, FlowEndPoint,
     IsMemTile, HasValidBDs, HasValidDMAChannels,
     DeclareOpInterfaceMethods<InferTypeOpInterface>
   ]>, Results<(outs Index)> {
@@ -1135,10 +1126,6 @@ def AIE_MemTileDMAOp: AIE_Op<"memtile_dma", [
     int colIndex();
     int rowIndex();
     TileOp getTileOp();
-    // CallableOpInterface
-    mlir::Region *getCallableRegion();
-    llvm::ArrayRef<mlir::Type> getArgumentTypes() { return getOperand().getType(); }
-    llvm::ArrayRef<mlir::Type> getResultTypes() { return getType(); }
     using ::xilinx::AIE::TileElement::Trait<MemTileDMAOp>::getAsmResultNames;
   }];
 }

include/aie/Dialect/AIE/IR/AIETargetModel.h

@@ -53,8 +53,31 @@ using TileID = struct TileID {
 };
 
 class AIETargetModel {
+
+public:
+  enum TargetModelKind {
+    TK_AIE1_VC1902,
+    TK_AIE1_Last,
+    TK_AIE2_VE2302,
+    TK_AIE2_VE2802,
+    TK_AIE2_NPU1,
+    TK_AIE2_NPU1_1Col,
+    TK_AIE2_NPU1_2Col,
+    TK_AIE2_NPU1_3Col,
+    TK_AIE2_NPU1_4Col,
+    TK_AIE2_NPU1_Last,
+    TK_AIE2_NPU2 = TK_AIE2_NPU1_Last,
+    TK_AIE2_NPU2_Last,
+    TK_AIE2_Last = TK_AIE2_NPU2_Last,
+  };
+
+private:
+  const TargetModelKind kind;
+
 public:
-  AIETargetModel() = default;
+  TargetModelKind getKind() const { return kind; }
+
+  AIETargetModel(TargetModelKind k) : kind(k) {}
 
   virtual ~AIETargetModel();
 
@@ -226,7 +249,7 @@ class AIETargetModel {
 
 class AIE1TargetModel : public AIETargetModel {
 public:
-  AIE1TargetModel() = default;
+  AIE1TargetModel(TargetModelKind k) : AIETargetModel(k) {}
 
   bool isCoreTile(int col, int row) const override { return row > 0; }
   bool isMemTile(int col, int row) const override { return false; }
@@ -286,11 +309,16 @@ class AIE1TargetModel : public AIETargetModel {
 
   uint32_t getColumnShift() const override { return 23; }
   uint32_t getRowShift() const override { return 18; }
+
+  static bool classof(const AIETargetModel *model) {
+    return model->getKind() >= TK_AIE1_VC1902 &&
+           model->getKind() < TK_AIE1_Last;
+  }
 };
 
 class AIE2TargetModel : public AIETargetModel {
 public:
-  AIE2TargetModel() = default;
+  AIE2TargetModel(TargetModelKind k) : AIETargetModel(k) {}
 
   AIEArch getTargetArch() const override;
 
@@ -363,14 +391,19 @@ class AIE2TargetModel : public AIETargetModel {
 
   uint32_t getColumnShift() const override { return 25; }
   uint32_t getRowShift() const override { return 20; }
+
+  static bool classof(const AIETargetModel *model) {
+    return model->getKind() >= TK_AIE2_VE2302 &&
+           model->getKind() < TK_AIE2_Last;
+  }
 };
 
 class VC1902TargetModel : public AIE1TargetModel {
   llvm::SmallDenseSet<unsigned, 16> nocColumns = {
       2, 3, 6, 7, 10, 11, 18, 19, 26, 27, 34, 35, 42, 43, 46, 47};
 
 public:
-  VC1902TargetModel() = default;
+  VC1902TargetModel() : AIE1TargetModel(TK_AIE1_VC1902) {}
 
   uint32_t getAddressGenGranularity() const override { return 32; }
 
@@ -389,13 +422,17 @@ class VC1902TargetModel : public AIE1TargetModel {
   bool isShimNOCorPLTile(int col, int row) const override {
     return isShimNOCTile(col, row) || isShimPLTile(col, row);
   }
+
+  static bool classof(const AIETargetModel *model) {
+    return model->getKind() == TK_AIE1_VC1902;
+  }
 };
 
 class VE2302TargetModel : public AIE2TargetModel {
   llvm::SmallDenseSet<unsigned, 8> nocColumns = {2, 3, 6, 7, 10, 11};
 
 public:
-  VE2302TargetModel() = default;
+  VE2302TargetModel() : AIE2TargetModel(TK_AIE2_VE2302) {}
 
   int columns() const override { return 17; }
 
@@ -419,14 +456,18 @@ class VE2302TargetModel : public AIE2TargetModel {
   }
 
   uint32_t getNumMemTileRows() const override { return 1; }
+
+  static bool classof(const AIETargetModel *model) {
+    return model->getKind() == TK_AIE2_VE2302;
+  }
 };
 
 class VE2802TargetModel : public AIE2TargetModel {
   llvm::SmallDenseSet<unsigned, 16> nocColumns = {2,  3,  6,  7,  14, 15,
                                                   22, 23, 30, 31, 34, 35};
 
 public:
-  VE2802TargetModel() = default;
+  VE2802TargetModel() : AIE2TargetModel(TK_AIE2_VE2802) {}
 
   int columns() const override { return 38; }
 
@@ -453,11 +494,15 @@ class VE2802TargetModel : public AIE2TargetModel {
   }
 
   uint32_t getNumMemTileRows() const override { return 2; }
+
+  static bool classof(const AIETargetModel *model) {
+    return model->getKind() == TK_AIE2_VE2802;
+  }
 };
 
 class BaseNPUTargetModel : public AIE2TargetModel {
 public:
-  BaseNPUTargetModel() = default;
+  BaseNPUTargetModel(TargetModelKind k) : AIE2TargetModel(k) {}
 
   int rows() const override {
     return 6; /* 1 Shim row, 1 memtile row, and 4 Core rows. */
@@ -481,12 +526,17 @@ class BaseNPUTargetModel : public AIE2TargetModel {
   virtual bool isVirtualized() const = 0;
 
   virtual bool isNPU() const override { return true; }
+
+  static bool classof(const AIETargetModel *model) {
+    return model->getKind() >= TK_AIE2_NPU1 &&
+           model->getKind() < TK_AIE2_NPU2_Last;
+  }
 };
 
 // The full Phoenix NPU
 class NPUTargetModel : public BaseNPUTargetModel {
 public:
-  NPUTargetModel() = default;
+  NPUTargetModel() : BaseNPUTargetModel(TK_AIE2_NPU1) {}
 
   int columns() const override { return 5; }
 
@@ -500,14 +550,22 @@ class NPUTargetModel : public BaseNPUTargetModel {
   }
 
   bool isVirtualized() const override { return false; }
+
+  static bool classof(const AIETargetModel *model) {
+    return model->getKind() == TK_AIE2_NPU1;
+  }
 };
 
 // A sub-portion of the NPU
 class VirtualizedNPUTargetModel : public BaseNPUTargetModel {
   int cols;
 
 public:
-  VirtualizedNPUTargetModel(int _cols) : cols(_cols) {}
+  VirtualizedNPUTargetModel(int _cols)
+      : BaseNPUTargetModel(static_cast<TargetModelKind>(
+            static_cast<std::underlying_type_t<TargetModelKind>>(TK_AIE2_NPU1) +
+            _cols)),
+        cols(_cols) {}
 
   uint32_t getAddressGenGranularity() const override { return 32; }
 
@@ -516,12 +574,17 @@ class VirtualizedNPUTargetModel : public BaseNPUTargetModel {
   bool isShimNOCTile(int col, int row) const override { return row == 0; }
 
   bool isVirtualized() const override { return true; }
+
+  static bool classof(const AIETargetModel *model) {
+    return model->getKind() >= TK_AIE2_NPU1_1Col &&
+           model->getKind() < TK_AIE2_NPU1_Last;
+  }
 };
 
 // The full Strix. NPU
 class NPU2TargetModel : public BaseNPUTargetModel {
 public:
-  NPU2TargetModel() = default;
+  NPU2TargetModel() : BaseNPUTargetModel(TK_AIE2_NPU2) {}
 
   AIEArch getTargetArch() const override;
 
@@ -532,6 +595,10 @@ class NPU2TargetModel : public BaseNPUTargetModel {
   bool isShimPLTile(int col, int row) const override { return false; }
 
   bool isVirtualized() const override { return false; }
+
+  static bool classof(const AIETargetModel *model) {
+    return model->getKind() == TK_AIE2_NPU2;
+  }
 };
 
 } // namespace xilinx::AIE

include/aie/Dialect/AIE/Transforms/AIEAssignBufferDescriptorIDs.h

@@ -11,27 +11,8 @@
 #ifndef AIE_ASSIGN_BUFFER_DESCRIPTOR_IDS_H
 #define AIE_ASSIGN_BUFFER_DESCRIPTOR_IDS_H
 
-#include <optional>
+#include "aie/Dialect/AIE/IR/AIETargetModel.h"
 
-#include "aie/Dialect/AIE/IR/AIEDialect.h"
-#include "aie/Dialect/AIE/Transforms/AIEAssignBufferDescriptorIDs.h"
-#include "aie/Dialect/AIE/Transforms/AIEPasses.h"
-
-#include "mlir/Pass/Pass.h"
-
-using namespace mlir;
-using namespace xilinx;
-using namespace xilinx::AIE;
-
-#include "aie/Dialect/AIE/IR/AIEDialect.h"
-#include "aie/Dialect/AIE/Transforms/AIEPasses.h"
-
-#include "mlir/Pass/Pass.h"
-
-#define DEBUG_TYPE "aie-assign-bd-ids"
-
-using namespace mlir;
-using namespace xilinx;
 using namespace xilinx::AIE;
 
 struct BdIdGenerator {
@@ -51,4 +32,4 @@ struct BdIdGenerator {
   void freeBdId(uint32_t bdId);
 };
 
-#endif
+#endif

include/aie/Dialect/AIE/Transforms/AIEGenerateColumnControlOverlay.h

@@ -11,26 +11,9 @@
 #ifndef AIE_ASSIGN_BUFFER_DESCRIPTOR_IDS_H
 #define AIE_ASSIGN_BUFFER_DESCRIPTOR_IDS_H
 
-#include <optional>
-
 #include "aie/Dialect/AIE/IR/AIEDialect.h"
-#include "aie/Dialect/AIE/Transforms/AIEPasses.h"
-
-#include "mlir/Pass/Pass.h"
-
-using namespace mlir;
-using namespace xilinx;
-using namespace xilinx::AIE;
-
-#include "aie/Dialect/AIE/IR/AIEDialect.h"
-#include "aie/Dialect/AIE/Transforms/AIEPasses.h"
-
-#include "mlir/Pass/Pass.h"
-
-#define DEBUG_TYPE "aie-generate-column-control-overlay"
 
 using namespace mlir;
-using namespace xilinx;
 using namespace xilinx::AIE;
 
 // Populate column control streaming interconnect overlay
@@ -44,7 +27,7 @@ DenseMap<int, int> getRowToShimChanMap(const AIETargetModel &targetModel,
 
 // AIE arch-specific tile id to controller id mapping. Users can use those
 // packet ids for design but run into risk of deadlocking control packet flows.
-DenseMap<AIE::TileID, int>
+DenseMap<TileID, int>
 getTileToControllerIdMap(bool clColumnWiseUniqueIDs,
                          const AIETargetModel &targetModel);