Merge pull request #740 from Xilinx/2023.1.2

2023.1.2
Xilinx · Jul 24, 2023 · 92eb05d · 92eb05d
2 parents fbc8e69 + d73091d
commit 92eb05d
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Showing 18 changed files with 862 additions and 145 deletions.
diff --git a/.classpath b/.classpath
@@ -33,9 +33,9 @@
 	<classpathentry kind="lib" path="jars/kryo-5.2.1.jar"/>
 	<classpathentry kind="lib" path="jars/minlog-1.3.1.jar"/>
 	<classpathentry kind="lib" path="jars/jython-standalone-2.7.2.jar"/>
-	<classpathentry kind="lib" path="jars/rapidwright-api-lib-2023.1.1.jar">
+	<classpathentry kind="lib" path="jars/rapidwright-api-lib-2023.1.2.jar">
 		<attributes>
-			<attribute name="javadoc_location" value="jar:platform:/resource/RapidWright/jars/rapidwright-api-lib-2023.1.1-javadoc.jar!/"/>
+			<attribute name="javadoc_location" value="jar:platform:/resource/RapidWright/jars/rapidwright-api-lib-2023.1.2-javadoc.jar!/"/>
 		</attributes>
 	</classpathentry>
 	<classpathentry kind="lib" path="jars/jgrapht-core-1.3.0.jar"/>

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
@@ -5,7 +5,7 @@ on:
   pull_request:
 
 env:
-  RAPIDWRIGHT_VERSION: v2023.1.1-beta
+  RAPIDWRIGHT_VERSION: v2023.1.2-beta
 
 jobs:
   build:

diff --git a/RELEASE_NOTES.TXT b/RELEASE_NOTES.TXT
@@ -1,3 +1,46 @@
+============= RapidWright 2023.1.2-beta released on 2023-07-24 ================
+Notes:
+  - Shell creation improvements to enable lock_design and timing closure preservation (#760)
+  - Adds a MakeBlackBox command line tool (#747)
+  - Removes the VCC A6 pin on 5LUT usages when removing cells (#741)
+  - Add DesignTools.getAllRoutedSitePinsFromPhysicalPin() (#755) 
+  - Correctly update dual-output route flags when unrouting (#737) 
+  - [PhysNetlistReader] Set cell type of LOCKED cells (#767)
+  - Updates RAM32X1S property to correct default (#751)
+  - [Interchange] PhysNetlistReader to create STATIC_SOURCE SiteInsts (#766)
+  - RWRoute Fixes (#765)
+  - GlobalSignalRouting.routeStaticNet() to create output SPIs (#761)
+  - DesignTools.createCeSrRstPinsToVCC() to skip non-SLICE FFs (#744)
+  - [PartialRouter] Improve incremental global routing (#759)
+  - GlobalSignalRouting fixes for routing to non clock-pins (#757)
+  - DesignTools.makePhysNetNamesConsistent() to merge static nets too (#753) 
+  - [UltraScaleClockRouting] Reset RouteNode.parent (#752)
+  - Created parameterizable counter with an adder as a submodule (#713)
+  - [RWRoute] Fix PartialRouter for when clk node already unpreserved (#746) 
+  - [Interchange] Fix PhysicalNetlist's MultiCellPinMapping (#743)
+  - Unroute site routing when removing a cell (#729)
+  - PartialRouter's global router to not unpreserve sink nodes (#736)
+  - DesignTools.makePhysNetNamesConsistent() to use hier name (#735)
+  - DesignTools.makePhysNetNamesConsistent() to consider */<const{0,1}> (#734)
+  - Add DcpToInterchange class (#704)
+  - Add compile step (#733)
+  - Add EdifToLogicalNetlist to MainEntrypoint (#731)
+  - Fix Javadoc warnings (#723)
+  - Fixes an issue with makeBlackBox trying to remove pins from renamed nets (#728)
+  - [PhysNetlistReader] Set Cell type for routethru cells (#727)
+  - Multilevel macro expansion (#726)
+  - TestReplaceEDIFInDCP to copy DCP before replacing in-place (#725)
+  - DesignTools.createMissingSitePinInsts() to skip node-less site pins (#724)
+  - Fix to create alternate source pins on dual output nets.
+  - Fixes incorrect Versal SLR corner tile entries
+  - Cell.getProperty() returns null if no EDIFCellInst found
+  - Cell.getAllSitePinsFromLogicalPin() to not return any null pins
+  - Cell.getAllCorrespondingSitePinNames() to not NPE if no physical pin mapping
+  - Cell.getCorrespondingSitePinName() to consider F?MUX routethrus
+- API Additions:
+  - com.xilinx.rapidwright.device.PIP "public boolean isLogicalDriver()"
+  - com.xilinx.rapidwright.design.Cell "public String getCorrespondingSitePinName(String logicalPinName, String physPinName, List<String> siteWires)"
+
 ============= RapidWright 2023.1.1-beta released on 2023-06-21 ================
 Notes:
   - UltraScale Incremental Clock Router Improvements (#540)

diff --git a/src/com/xilinx/rapidwright/MainEntrypoint.java b/src/com/xilinx/rapidwright/MainEntrypoint.java
@@ -95,6 +95,7 @@
 import com.xilinx.rapidwright.util.FileTools;
 import com.xilinx.rapidwright.util.JobQueue;
 import com.xilinx.rapidwright.util.Jython;
+import com.xilinx.rapidwright.util.MakeBlackBox;
 import com.xilinx.rapidwright.util.PartPrinter;
 import com.xilinx.rapidwright.util.PerformanceExplorer;
 import com.xilinx.rapidwright.util.ReplaceEDIFInDCP;
@@ -152,6 +153,7 @@ private static void addFunction(String name, MainStyleFunction<?> func) {
         addFunction("Lesson1", Lesson1::main);
         addFunction("LogicalNetlistExample", LogicalNetlistExample::main);
         addFunction("LUTTools", LUTTools::main);
+        addFunction("MakeBlackBox", MakeBlackBox::main);
         addFunction("MergeDesigns", MergeDesigns::main);
         addFunction("MetadataParser", MetadataParser::main);
         addFunction("ModuleOptimizer", ModuleOptimizer::main);