[Vivado][Yosys] Quote source filename in case their paths contain spaces

pyproject.toml

@@ -39,7 +39,7 @@ dependencies = [
  "jinja2 ~= 3.1",
  "pydantic >= 1.10, < 2.0",
  "tomli ~= 2.0; python_version<'3.11'",
- "python-box[] ~= 7.0",
+ "python-box[] ~= 7.2",
  "attrs >= 22.1,< 24.0",
  "cattrs >= 22.2,< 24.0",
  "attrs_strict ~= 1.0",
@@ -49,21 +49,21 @@ dependencies = [
  "coloredlogs ~= 15.0",
  "rich >= 12.6,< 14.0",
  "pebble ~= 5.0",
- "pint ~= 0.20",
+ "pint ~= 0.24",
  "importlib_resources >= 5.10", # backport of importlib.resources, replaces pkg_resources
- "simpleeval >= 0.9.13",
+ "simpleeval ~= 0.9",
  # experimental:
- "pyyaml >= 6.0",
- "varname >= 0.10",
- "overrides >= 6.1",
- "simple_term_menu >= 1.5.2",
- "psutil >= 5.9",
+ "pyyaml ~= 6.0",
+ "varname ~= 0.13",
+ "overrides ~= 7.7",
+ "simple_term_menu ~= 1.6",
+ "psutil ~= 6.0",
  "junitparser >= 2.4,< 4.0", # TODO: remove
- "pyvcd ~= 0.3",
- "GitPython >= 3.1.30",
- "fabric >= 3.1.0",
- "execnet >= 2.1.1",
- "devtools >= 0.11",
+ "pyvcd ~= 0.4",
+ "GitPython ~= 3.1",
+ "fabric ~= 3.2",
+ "execnet ~= 2.1",
+ "devtools ~= 0.12",
 ]
 
 [project.optional-dependencies]

src/xeda/flow/flow.py

@@ -254,6 +254,7 @@ def __init__(self, settings: Settings, design: Design, run_path: Path):
  self.artifacts = Box()
  self.results = self.Results()
  self.jinja_env = self._create_jinja_env(extra_modules=[self.__module__])
+ self.add_template_filter("quote", lambda x: f'"{x}"')
  self.add_template_test("match", regex_match)
  self.dependencies: List[Tuple[Union[Type["Flow"], str], Flow.Settings, List[str]]] = []
  self.completed_dependencies: List[Flow] = []
@@ -304,10 +305,11 @@ def copy_from_template(
  f.write(rendered_content)
  return script_path.resolve().relative_to(self.run_path)
 
- def add_template_filter(self, filter_name: str, func) -> None:
+ def add_template_filter(self, filter_name: str, func, replace_existing=False) -> None:
  assert filter_name
  if filter_name in self.jinja_env.filters:
- raise ValueError(f"Template filter with name {filter_name} already exists!")
+ if not replace_existing:
+ raise ValueError(f"Template filter with name {filter_name} already exists!")
  self.jinja_env.filters[filter_name] = func
 
  def add_template_filter_func(self, func) -> None:

src/xeda/flows/vivado/templates/vivado_alt_synth.tcl

@@ -39,17 +39,17 @@ puts "Targeting device: $fpga_part"
 {% for src in design.rtl.sources %}
 {% if src.type.name == "Verilog" %}
 puts "Reading Verilog file {{src.file}}"
-if { [catch {eval read_verilog {{src.file}} } myError]} {
+if { [catch {eval read_verilog \"{{src.file}}\" } myError]} {
  errorExit $myError
 }
 {%- elif src.type.name == "SystemVerilog" %}
 puts "Reading SystemVerilog file {{src.file}}"
-if { [catch {eval read_verilog -sv {{src.file}} } myError]} {
+if { [catch {eval read_verilog -sv \"{{src.file}}\" } myError]} {
  errorExit $myError
 }
 {%- elif src.type.name == "Vhdl" %}
 puts "Reading VHDL file {{src.file}}"
-if { [catch {eval read_vhdl {% if design.language.vhdl.standard == "08" %} -vhdl2008 {%- endif %} {{src.file}} } myError]} {
+if { [catch {eval read_vhdl {% if design.language.vhdl.standard == "08" %} -vhdl2008 {%- endif %} \"{{src.file}}\" } myError]} {
  errorExit $myError
 }
 {%- endif %}

src/xeda/flows/vivado/templates/vivado_sim.tcl

@@ -19,17 +19,17 @@ puts "\n===========================( Analyzing HDL Sources )====================
 {%- for src in design.sim_sources %}
 {%- if src.type.name == "Verilog" %}
 puts "Analyzing Verilog file {{src.file}}"
-if { [catch {eval exec xvlog ${analyze_flags} {{src.file}} } error]} {
+if { [catch {eval exec xvlog ${analyze_flags} \"{{src.file}}\" } error]} {
  errorExit $error
 }
 {%- elif src.type.name == "SystemVerilog" %}
 puts "Analyzing SystemVerilog file {{src.file}}"
-if { [catch {eval exec xvlog ${analyze_flags} -sv {{src.file}} } error]} {
+if { [catch {eval exec xvlog ${analyze_flags} -sv \"{{src.file}}\" } error]} {
  errorExit $error
 }
 {%- elif src.type.name == "Vhdl" %}
 puts "Analyzing VHDL file {{src.file}} VHDL Standard: {{design.language.vhdl.standard}}"
-if { [catch {eval exec xvhdl ${analyze_flags} {% if design.language.vhdl.standard == "08" %} -2008 {% elif design.language.vhdl.standard == "93" %} -93_mode {% endif %} {{src.file}} } error]} {
+if { [catch {eval exec xvhdl ${analyze_flags} {% if design.language.vhdl.standard == "08" %} -2008 {% elif design.language.vhdl.standard == "93" %} -93_mode {% endif %} \"{{src.file}}\" } error]} {
  errorExit $error
 }
 {%- endif %}

src/xeda/flows/vivado/templates/vivado_synth.tcl

@@ -15,17 +15,17 @@ puts "\n=====================( Read Design Files and Constraints )==============
 {%- for src in design.rtl.sources %}
 {%- if src.type.name == "Verilog" %}
 puts "Reading Verilog file {{src.file}}"
-if { [catch {eval read_verilog {{src.file}} } myError]} {
+if { [catch {eval read_verilog \"{{src.file}}\" } myError]} {
  errorExit $myError
 }
 {%- elif src.type.name == "SystemVerilog" %}
 puts "Reading SystemVerilog file {{src.file}}"
-if { [catch {eval read_verilog -sv {{src.file}} } myError]} {
+if { [catch {eval read_verilog -sv \"{{src.file}}\" } myError]} {
  errorExit $myError
 }
 {%- elif src.type.name == "Vhdl" %}
 puts "Reading VHDL file {{src.file}}"
-if { [catch {eval read_vhdl {% if design.language.vhdl.standard == "08" or design.language.vhdl.standard == "2008" %} -vhdl2008 {%- endif %} {{src.file}} } myError]} {
+if { [catch {eval read_vhdl {% if design.language.vhdl.standard == "08" or design.language.vhdl.standard == "2008" %} -vhdl2008 {%- endif %} \"{{src.file}}\" } myError]} {
  errorExit $myError
 }
 {%- endif %}

src/xeda/flows/vivado/vivado_sim.py

@@ -46,7 +46,7 @@ def run(self) -> None:
  ss.elab_flags.append(f"-debug {elab_debug}")
 
  assert self.design.tb
- assert self.design.sim_tops, "tb.top was not specified"
+ # assert self.design.sim_tops, "tb.top was not specified"
  if ss.vcd:
  log.info("Dumping VCD to %s", self.run_path / ss.vcd)
  sdf_root = ss.sdf.root

src/xeda/flows/yosys/common.py

@@ -190,8 +190,8 @@ def init(self):
  ss.flatten = True # design must be flattened
  if ss.flatten:
  append_flag(ss.synth_flags, "-flatten")
- if ss.flatten:
- append_flag(ss.synth_flags, "-flatten")
+ else:
+ append_flag(ss.synth_flags, "-noflatten")
  if ss.abc_dff:
  append_flag(ss.abc_flags, "-dff")
  ss.set_attribute = hierarchical_merge(self.design.rtl.attributes, ss.set_attribute)

src/xeda/flows/yosys/templates/read_files.tcl

@@ -12,18 +12,19 @@ yosys plugin -i systemverilog
 {%- for src in design.rtl.sources %}
 {%- if src.type.name == "Verilog" or (not uhdm_plugin and src.type.name == "SystemVerilog") %}
 yosys log -stdout "** Reading {{src}} **"
-yosys read_verilog -defer {{settings.read_verilog_flags|join(" ")}} {{defines|join(" ")}} {{src}}
+yosys read_verilog -defer {{settings.read_verilog_flags|join(" ")}} {{defines|join(" ")}} "{{src}}"
 {%- elif src.type.name == "SystemVerilog" %}
 yosys log -stdout "** Reading {{src}} **"
-yosys read_systemverilog -defer {{settings.read_systemverilog_flags|join(" ")}} {{src}}
+yosys read_systemverilog -defer {{settings.read_systemverilog_flags|join(" ")}} "{{src}}"
 {%- endif %}
 {%- endfor %}
 
-{% set vhdl_files = design.sources_of_type("Vhdl", rtl=true, tb=false) %}
+{% set vhdl_files = design.sources_of_type("Vhdl", rtl=true, tb=false) | map('quote') %}
 {%- if vhdl_files %}
 yosys log -stdout "** Elaborating VHDL files **"
 yosys plugin -i ghdl
-yosys ghdl {{ghdl_args|join(" ")}}
+set ghdl_args "{{ghdl_args|join(" ")}}"
+yosys ghdl {*}$ghdl_args {{vhdl_files|join (" ")}} -e
 {% endif %}
 
 {%- if settings.liberty is defined %}
@@ -33,7 +34,7 @@ yosys read_liberty -lib {{lib}}
 {%- endif %}
 
 {%- for src in settings.verilog_lib %}
-yosys read_verilog -lib {{src}}
+yosys read_verilog -lib "{{src}}"
 {% endfor %}
 
 {%- for key, value in parameters.items() %}

src/xeda/flows/yosys/yosys.py

@@ -271,7 +271,7 @@ def set_file_path(p):
  "yosys_synth.tcl",
  lstrip_blocks=True,
  trim_blocks=False,
- ghdl_args=GhdlSynth.synth_args(ss.ghdl, self.design),
+ ghdl_args=GhdlSynth.synth_args(ss.ghdl, self.design, one_shot_elab=False),
  parameters=process_parameters(self.design.rtl.parameters),
  defines=[f"-D{k}" if v is None else f"-D{k}={v}" for k, v in ss.defines.items()],
  abc_constr_file=abc_constr_file,

src/xeda/flows/yosys/yosys_fpga.py

@@ -106,7 +106,7 @@ def run(self) -> None:
  "yosys_fpga_synth.tcl",
  lstrip_blocks=True,
  trim_blocks=False,
- ghdl_args=GhdlSynth.synth_args(ss.ghdl, self.design),
+ ghdl_args=GhdlSynth.synth_args(ss.ghdl, self.design, one_shot_elab=False),
  parameters=process_parameters(self.design.rtl.parameters),
  defines=[f"-D{k}" if v is None else f"-D{k}={v}" for k, v in ss.defines.items()],
  abc_constr_file=abc_constr_file,

tests/test_vivado.py

@@ -26,7 +26,7 @@ def test_vivado_synth_template() -> None:
  "vivado_synth.tcl",
  xdc_files=[],
  reports_tcl="reports_tcl",
- generics=" ".join(vivado_synth_generics(design)),
+ generics=" ".join(vivado_synth_generics(design.rtl.parameters)),
  )
  with open(run_dir / tcl_file) as f:
  vivado_tcl = f.read()
@@ -44,10 +44,11 @@ def test_vivado_synth_py() -> None:
  assert path.exists()
  design = Design.from_toml(EXAMPLES_DIR / "vhdl" / "sqrt" / "sqrt.toml")
  settings = dict(fpga=FPGA("xc7a12tcsg325-1"), clock_period=5.5)
- with tempfile.TemporaryDirectory() as run_dir:
+ with tempfile.TemporaryDirectory(dir=Path.cwd()) as run_dir:
  print("Xeda run dir: ", run_dir)
  xeda_runner = DefaultRunner(run_dir, debug=True)
  flow = xeda_runner.run_flow(VivadoSynth, design, settings)
+ assert flow is not None, "run_flow returned None"
  settings_json = flow.run_path / "settings.json"
  results_json = flow.run_path / "results.json"
  assert settings_json.exists()