…acks

…acks

…nto 162-add-support-for-gf180-mcu

add -ignore_mismatches

Add quickstart to main documentation

remove install caravel section

update PDK

update variable for verify

add def for reg_mprj_slave

162 add support for gf180 mcu

Corrected PDK variable for gf180

docs: fix intrapage link

user_project_wrapper fix

clone timing-scripts
setup venv
generate_spef_mapping
TODO: extract modules inside user_project_wrapper

fetches the macros and extract parasitics for them
~ suppress makefile shell commands

diff --git a/Makefile b/Makefile
index 42b616a..4e2176a 100644
--- a/Makefile
+++ b/Makefile
@@ -262,36 +262,50 @@ help:

 export CUP_ROOT=$(shell pwd)
-export TIMING_ROOT=$(shell pwd)/deps/timing-scripts
-export CURRENT_PROJECT=$(CUP_ROOT)
+export TIMING_ROOT?=$(shell pwd)/deps/timing-scripts
+export PROJECT_ROOT=$(CUP_ROOT)
 [email protected]:efabless/timing-scripts.git

 $(TIMING_ROOT):
-	git clone $(timing-scripts-repo) $(TIMING_ROOT)
+	@git clone $(timing-scripts-repo) $(TIMING_ROOT)

 .PHONY: setup-timing-scripts
 setup-timing-scripts: $(TIMING_ROOT)
-	( cd $(TIMING_ROOT) && git pull )
+	@( cd $(TIMING_ROOT) && git pull )
 	#( cd $(TIMING_ROOT) && git fetch && git checkout $(MPW_TAG); )
-	python3 -m venv ./venv
-	. ./venv/bin/activate && \
-	python3 -m pip install --upgrade pip && \
-	python3 -m pip install -r $(TIMING_ROOT)/requirements.txt && \
-	deactivate
+	@python3 -m venv ./venv
+		. ./venv/bin/activate && \
+		python3 -m pip install --upgrade pip && \
+		python3 -m pip install -r $(TIMING_ROOT)/requirements.txt && \
+		deactivate

 ./verilog/gl/user_project_wrapper.v:
 	$(error you don't have $@)

-./env/spef-mapping.tcl: $(setup-timing-scripts) ./verilog/gl/user_project_wrapper.v
-	. ./venv/bin/activate && \
-	python3 $(TIMING_ROOT)/scripts/generate_spef_mapping.py \
-		-i ./verilog/gl/user_project_wrapper.v \
-		-o ./env/spef-mapping.tcl \
-		--pdk $(PDK) \
-		--pdk-root $(PDK_ROOT) \
-		--project-root '$$::env(CUP_ROOT)' && \
+./env/spef-mapping.tcl: $(TIMING_ROOT) ./verilog/gl/user_project_wrapper.v
+	@. ./venv/bin/activate && \
+		python3 $(TIMING_ROOT)/scripts/generate_spef_mapping.py \
+			-i ./verilog/gl/user_project_wrapper.v \
+			-o ./env/spef-mapping.tcl \
+			--pdk-path $(PDK_ROOT)/$(PDK) \
+			--project-root "$(CUP_ROOT)" && \
+		deactivate
+
+.PHONY: extract-parasitics
+extract-parasitics: $(TIMING_ROOT) ./verilog/gl/user_project_wrapper.v
+	@. ./venv/bin/activate && \
+	python3 $(TIMING_ROOT)/scripts/get_macros.py \
+	-i ./verilog/gl/user_project_wrapper.v \
+	-o ./tmp-macros-list \
+	--pdk-path $(PDK_ROOT)/$(PDK) && \
 	deactivate
+	@cat ./tmp-macros-list | cut -d " " -f2 \
+		| xargs -I % bash -c "$(MAKE) -C $(TIMING_ROOT) \
+			-f $(TIMING_ROOT)/timing.mk rcx-% || echo 'Cannot extract %. Probably no def for this macro'"
+

 .PHONY: caravel-sta
 caravel-sta: ./env/spef-mapping.tcl
-	$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-typ-nom
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-nom
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-fast
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-slow

remove components and nets section from template def

Merging all recent changes from main branch.

definitions that are not used in the caravan project (although that is
not relevant here).  Only changed comment lines.

Correct the user_defines.v GPIO configuration definitions

integrate timing-scripts for opensta

update openlane to correct pdn drc issue

Update Makefile

…ction

documentation for GPIO configuration

openlane/user_project_wrapper: rename deprecated config

openlane/user_project_wrapper: use string var

openlane/user_project_wrapper_gf180mcu: remove components and nets section

Timing scripts report summary

use docker for python timing-scripts

changed 130B to 130A