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Use DESIGN HOME variable in config.mk #2546

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Use DESIGN HOME variable in config.mk #2546

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4 changes: 2 additions & 2 deletions flow/designs/asap7/aes-block/config.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,8 @@ export PLATFORM = asap7
export DESIGN_NAME = aes_cipher_top
export DESIGN_NICKNAME = aes-block

export VERILOG_FILES = $(sort $(wildcard ./designs/src/aes/*.v))
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/aes/*.v))
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

export ABC_AREA = 1

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4 changes: 2 additions & 2 deletions flow/designs/asap7/aes-mbff/config.mk
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Expand Up @@ -3,8 +3,8 @@ export PLATFORM = asap7
export DESIGN_NAME = aes_cipher_top
export DESIGN_NICKNAME = aes-mbff

export VERILOG_FILES = $(sort $(wildcard ./designs/src/aes/*.v))
export SDC_FILE = ./designs/$(PLATFORM)/aes/constraint.sdc
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/aes/*.v))
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/aes/constraint.sdc

export ABC_AREA = 1

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4 changes: 2 additions & 2 deletions flow/designs/asap7/aes/config.mk
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Expand Up @@ -3,8 +3,8 @@ export PLATFORM = asap7
export DESIGN_NAME = aes_cipher_top
export DESIGN_NICKNAME = aes

export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

export ABC_AREA = 1

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4 changes: 2 additions & 2 deletions flow/designs/asap7/aes_lvt/config.mk
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Expand Up @@ -3,8 +3,8 @@ export PLATFORM = asap7
export DESIGN_NAME = aes_cipher_top
export DESIGN_NICKNAME = aes_lvt

export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

export ABC_AREA = 1

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4 changes: 2 additions & 2 deletions flow/designs/asap7/ethmac/config.mk
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Expand Up @@ -2,8 +2,8 @@ export PLATFORM = asap7

export DESIGN_NAME = ethmac

export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export ABC_AREA = 1

export CORE_UTILIZATION = 40
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4 changes: 2 additions & 2 deletions flow/designs/asap7/ethmac_lvt/config.mk
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Expand Up @@ -3,8 +3,8 @@ export PLATFORM = asap7
export DESIGN_NAME = ethmac
export DESIGN_NICKNAME = ethmac_lvt

export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export ABC_AREA = 1

export CORE_UTILIZATION = 40
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4 changes: 2 additions & 2 deletions flow/designs/asap7/gcd/config.mk
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Expand Up @@ -2,8 +2,8 @@ export PLATFORM = asap7

export DESIGN_NAME = gcd

export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NAME)/*.v))
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NAME)/*.v))
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc

export DIE_AREA = 0 0 16.2 16.2
export CORE_AREA = 1.08 1.08 15.12 15.12
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4 changes: 2 additions & 2 deletions flow/designs/asap7/ibex/config.mk
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Expand Up @@ -3,8 +3,8 @@ export PLATFORM = asap7
export DESIGN_NICKNAME = ibex
export DESIGN_NAME = ibex_core

export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

export CORE_UTILIZATION = 40
export CORE_ASPECT_RATIO = 1
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6 changes: 3 additions & 3 deletions flow/designs/asap7/jpeg/config.mk
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Expand Up @@ -3,9 +3,9 @@ export PLATFORM = asap7
export DESIGN_NAME = jpeg_encoder
export DESIGN_NICKNAME = jpeg

export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc
export ABC_AREA = 1

export CORE_UTILIZATION = 30
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6 changes: 3 additions & 3 deletions flow/designs/asap7/jpeg_lvt/config.mk
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Expand Up @@ -3,9 +3,9 @@ export PLATFORM = asap7
export DESIGN_NAME = jpeg_encoder
export DESIGN_NICKNAME = jpeg_lvt

export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc
export ABC_AREA = 1

export ADDITIONAL_LIBS = $(LIB_DIR)/asap7sc7p5t_AO_LVT_FF_nldm_211120.lib.gz \
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6 changes: 3 additions & 3 deletions flow/designs/asap7/mock-array/config.mk
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Expand Up @@ -32,7 +32,7 @@ export BLOCKS ?= Element
ifneq ($(BLOCKS),)
export GDS_ALLOW_EMPTY = Element
ifneq ($(RTLMP_FLOW), 1)
export MACRO_PLACEMENT_TCL = ./designs/asap7/mock-array/macro-placement.tcl
export MACRO_PLACEMENT_TCL = $(DESIGN_HOME)/asap7/mock-array/macro-placement.tcl
endif
export PDN_TCL = $(PLATFORM_DIR)/openRoad/pdn/BLOCKS_grid_strategy.tcl
endif
Expand All @@ -44,13 +44,13 @@ export IO_CONSTRAINTS = designs/asap7/mock-array/io.tcl
verilog:
export MOCK_ARRAY_ROWS=$(word 1, $(MOCK_ARRAY_TABLE)) ; \
export MOCK_ARRAY_COLS=$(word 2, $(MOCK_ARRAY_TABLE)) ; \
./designs/asap7/mock-array/verilog.sh
$(DESIGN_HOME)/asap7/mock-array/verilog.sh

.PHONY: simulate
simulate:
export MOCK_ARRAY_ROWS=$(word 1, $(MOCK_ARRAY_TABLE)) ; \
export MOCK_ARRAY_COLS=$(word 2, $(MOCK_ARRAY_TABLE)) ; \
./designs/asap7/mock-array/simulate.sh
$(DESIGN_HOME)/asap7/mock-array/simulate.sh

.PHONY: power
power:
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4 changes: 2 additions & 2 deletions flow/designs/asap7/mock-cpu/config.mk
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Expand Up @@ -3,8 +3,8 @@ export PLATFORM = asap7
export DESIGN_NAME = mock_cpu
export DESIGN_NICKNAME = mock-cpu

export VERILOG_FILES = $(wildcard ./designs/src/fifo/*.v)
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export VERILOG_FILES = $(wildcard $(DESIGN_HOME)/src/fifo/*.v)
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

export CORE_UTILIZATION = 40
export CORE_ASPECT_RATIO = 1
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4 changes: 2 additions & 2 deletions flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/config.mk
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Expand Up @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = riscv32i-mock-sram_fakeram7_256x32
export DESIGN_NAME = fakeram7_256x32
export PLATFORM = asap7

export VERILOG_FILES = ./designs/asap7/riscv32i-mock-sram/fakeram7_256x32/*.v
export SDC_FILE = ./designs/$(PLATFORM)/riscv32i-mock-sram/fakeram7_256x32/constraints.sdc
export VERILOG_FILES = $(DESIGN_HOME)/asap7/riscv32i-mock-sram/fakeram7_256x32/*.v
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/riscv32i-mock-sram/fakeram7_256x32/constraints.sdc

export CORE_UTILIZATION = 50
export CORE_ASPECT_RATIO = 8
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4 changes: 2 additions & 2 deletions flow/designs/asap7/riscv32i/config.mk
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Expand Up @@ -11,8 +11,8 @@ export RTLMP_MAX_MACRO = 5

export MAX_UNGROUP_SIZE ?= 1000

export VERILOG_FILES = $(sort $(wildcard ./designs/src/riscv32i/*.v))
export SDC_FILE = ./designs/$(PLATFORM)/riscv32i/constraint.sdc
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/riscv32i/*.v))
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/riscv32i/constraint.sdc

ifeq ($(BLOCKS),)
export ADDITIONAL_LEFS = ./platforms/$(PLATFORM)/lef/fakeram7_256x32.lef
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10 changes: 5 additions & 5 deletions flow/designs/asap7/swerv_wrapper/config.mk
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Expand Up @@ -10,12 +10,12 @@ export RTLMP_MIN_MACRO = 4

export LIB_MODEL = CCS

export VERILOG_FILES = ./designs/src/swerv/swerv_wrapper.sv2v.v \
./designs/$(PLATFORM)/swerv_wrapper/macros.v
export SDC_FILE = ./designs/$(PLATFORM)/swerv_wrapper/constraint.sdc
export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \
$(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/macros.v
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/constraint.sdc

export ADDITIONAL_LEFS = $(sort $(wildcard ./designs/$(PLATFORM)/swerv_wrapper/lef/*.lef))
export ADDITIONAL_LIBS = $(sort $(wildcard ./designs/$(PLATFORM)/swerv_wrapper/lib/*.lib))
export ADDITIONAL_LEFS = $(sort $(wildcard $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/lef/*.lef))
export ADDITIONAL_LIBS = $(sort $(wildcard $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/lib/*.lib))

export DIE_AREA = 0 0 550 600
export CORE_AREA = 5 5 545 595
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4 changes: 2 additions & 2 deletions flow/designs/asap7/uart/config.mk
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Expand Up @@ -3,8 +3,8 @@ export CORNER = TC

export DESIGN_NAME = uart

export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

export PLACE_DENSITY = 0.70
export DIE_AREA = 0 0 17 17
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4 changes: 2 additions & 2 deletions flow/designs/gf12/aes/config.mk
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Expand Up @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = aes
export DESIGN_NAME = aes_cipher_top
export PLATFORM = gf12

export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export ABC_AREA = 1

export CORE_UTILIZATION = 40
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10 changes: 5 additions & 5 deletions flow/designs/gf12/ariane/config.mk
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Expand Up @@ -5,11 +5,11 @@ export SYNTH_HIERARCHICAL = 1
export MAX_UNGROUP_SIZE ?= 10000
#

export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/ariane.sv2v.v \
./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/ariane.sv2v.v \
$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v

#export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint_hier.sdc
#export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint_hier.sdc

export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12lp_1rf_lg8_w64_byte.lef

Expand All @@ -27,7 +27,7 @@ export PLACE_PINS_ARGS = -exclude left:0-150 -exclude left:450-600 -exclude righ
export MACRO_PLACE_HALO = 7 7
export MACRO_PLACE_CHANNEL = 14 14

export MACRO_WRAPPERS = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl
export MACRO_WRAPPERS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl

ifeq ($(USE_FILL),1)
export DESIGN_TYPE = CELL
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2 changes: 1 addition & 1 deletion flow/designs/gf12/ariane133/config.mk
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Expand Up @@ -9,7 +9,7 @@ export MAX_UNGROUP_SIZE ?= 10000

export VERILOG_FILES = $(PLATFORM_DIR)/ariane133/ariane.v

export SDC_FILE = ./designs/$(PLATFORM)/ariane133/ariane.sdc
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/ariane133/ariane.sdc

export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1rw_256x16.lef
export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1rw_256x16_ffpg_sigcmin_0p88v_0p88v_m40c.lib
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2 changes: 1 addition & 1 deletion flow/designs/gf12/bp_single/config.mk
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Expand Up @@ -61,7 +61,7 @@ export MACRO_PLACEMENT = $(PLATFORM_DIR)/bp/auto_fence2_bp_single.macro_placment
export MACRO_BLOCKAGE_HALO = 25

export PDN_TCL = $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl
export FASTROUTE_TCL = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl
export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl

ifeq ($(USE_FILL),1)
export DESIGN_TYPE = CHIP
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8 changes: 4 additions & 4 deletions flow/designs/gf12/coyote/config.mk
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Expand Up @@ -2,10 +2,10 @@ export DESIGN_NICKNAME = coyote
export DESIGN_NAME = bsg_rocket_node_client_rocc
export PLATFORM = gf12

export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/coyote.sv2v.v \
./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/coyote.sv2v.v \
$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v

export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export ABC_AREA = 1

export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1rf_lg6_w80_bit.lef \
Expand All @@ -25,7 +25,7 @@ export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1rf_lg6_w80_bit.gds2 \

export PLACE_DENSITY = 0.35

export MACRO_WRAPPERS = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl
export MACRO_WRAPPERS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/wrappers.tcl

export DIE_AREA = 0 0 752 752
export CORE_AREA = 2 2 750 750
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4 changes: 2 additions & 2 deletions flow/designs/gf12/gcd/config.mk
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Expand Up @@ -2,8 +2,8 @@ export DESIGN_NICKNAME = gcd_$(TRACK_OPTION)_$(TECH_OPTION)
export DESIGN_NAME = gcd
export PLATFORM = gf12

export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/gcd.v
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc

# These values must be multiples of placement site
export DIE_AREA = 0 0 99.96 100.128
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82 changes: 41 additions & 41 deletions flow/designs/gf12/ibex/config.mk
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Expand Up @@ -3,47 +3,47 @@ export DESIGN_NAME = ibex_core
export PLATFORM = gf12


export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/ibex_alu.v \
./designs/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \
./designs/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \
./designs/src/$(DESIGN_NICKNAME)/ibex_controller.v \
./designs/src/$(DESIGN_NICKNAME)/ibex_core.v \
./designs/src/$(DESIGN_NICKNAME)/ibex_counter.v \
./designs/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \
./designs/src/$(DESIGN_NICKNAME)/ibex_csr.v \
./designs/src/$(DESIGN_NICKNAME)/ibex_decoder.v \
./designs/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \
./designs/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \
./designs/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \
./designs/src/$(DESIGN_NICKNAME)/ibex_icache.v \
./designs/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \
./designs/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \
./designs/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \
./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \
./designs/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \
./designs/src/$(DESIGN_NICKNAME)/ibex_pmp.v \
./designs/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \
./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \
./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \
./designs/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \
./designs/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \
./designs/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \
./designs/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \
./designs/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \
./designs/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \
./designs/src/$(DESIGN_NICKNAME)/prim_lfsr.v \
./designs/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \
./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \
./designs/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \
./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \
./designs/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \
./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \
./designs/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \
./designs/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v



export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v



export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

export CORE_UTILIZATION = 40
export CORE_ASPECT_RATIO = 1
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