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initial scaffold for tunable variables
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Signed-off-by: Jack Luar <[email protected]>
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luarss committed Oct 12, 2024
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42 changes: 30 additions & 12 deletions docs/user/FlowVariables.md
Original file line number Diff line number Diff line change
Expand Up @@ -100,6 +100,7 @@ configuration file.
| <a name="GPL_TIMING_DRIVEN"></a>GPL_TIMING_DRIVEN| Specifies whether the placer should use timing driven placement.| |
| <a name="GUI_TIMING"></a>GUI_TIMING| Load timing information when opening GUI. For large designs, this can be quite time consuming. Useful to disable when investigating non-timing aspects like floorplan, placement, routing, etc.| |
| <a name="HOLD_SLACK_MARGIN"></a>HOLD_SLACK_MARGIN| Specifies a time margin for the slack when fixing hold violations. This option allows you to overfix.| |
| <a name="IO_CONSTRAINTS"></a>IO_CONSTRAINTS| File path to the IO constraints .tcl file.| |
| <a name="IO_PLACER_H"></a>IO_PLACER_H| The metal layer on which to place the I/O pins horizontally (top and bottom of the die).| |
| <a name="IO_PLACER_V"></a>IO_PLACER_V| The metal layer on which to place the I/O pins vertically (sides of the die).| |
| <a name="IR_DROP_LAYER"></a>IR_DROP_LAYER| Default metal layer to report IR drop.| |
Expand All @@ -123,6 +124,7 @@ configuration file.
| <a name="PDN_TCL"></a>PDN_TCL| File path which has a set of power grid policies used by pdn to be applied to the design, such as layers to use, stripe width and spacing to generate the actual metal straps.| |
| <a name="PLACE_DENSITY"></a>PLACE_DENSITY| The desired placement density of cells. It reflects how spread the cells would be on the core area. 1.0 = closely dense. 0.0 = widely spread.| |
| <a name="PLACE_DENSITY_LB_ADDON"></a>PLACE_DENSITY_LB_ADDON| Check the lower boundary of the PLACE_DENSITY and add PLACE_DENSITY_LB_ADDON if it exists.| |
| <a name="PLACE_PINS_ARGS"></a>PLACE_PINS_ARGS| Arguments to place_pins| |
| <a name="PLACE_SITE"></a>PLACE_SITE| Placement site for core cells defined in the technology LEF file.| |
| <a name="PLATFORM"></a>PLATFORM| Specifies process design kit or technology node to be used.| |
| <a name="POST_CTS_TCL"></a>POST_CTS_TCL| Specifies a Tcl script with commands to run after CTS is completed.| |
Expand All @@ -131,6 +133,7 @@ configuration file.
| <a name="PWR_NETS_VOLTAGES"></a>PWR_NETS_VOLTAGES| Used for IR Drop calculation.| |
| <a name="RCX_RULES"></a>RCX_RULES| RC Extraction rules file path.| |
| <a name="RECOVER_POWER"></a>RECOVER_POWER| Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100].| 0 |
| <a name="REMOVE_ABC_BUFFERS"></a>REMOVE_ABC_BUFFERS| Remove abc buffers from the netlist.| |
| <a name="REMOVE_CELLS_FOR_EQY"></a>REMOVE_CELLS_FOR_EQY| String patterns directly passed to write_verilog -remove_cells <> for equivalence checks.| |
| <a name="REPAIR_PDN_VIA_LAYER"></a>REPAIR_PDN_VIA_LAYER| Remove power grid vias which generate DRC violations after detailed routing.| |
| <a name="RESYNTH_AREA_RECOVER"></a>RESYNTH_AREA_RECOVER| Enable re-synthesis for area reclaim.| |
Expand All @@ -139,6 +142,7 @@ configuration file.
| <a name="RTLMP_FLOW"></a>RTLMP_FLOW| 1 to enable the Hierarchical RTLMP flow, default empty.| |
| <a name="SC_LEF"></a>SC_LEF| Path to technology standard cell LEF file.| |
| <a name="SDC_FILE"></a>SDC_FILE| The path to design constraint (SDC) file.| |
| <a name="SDC_GUT"></a>SDC_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| |
| <a name="SEAL_GDS"></a>SEAL_GDS| Seal macro to place around the design.| |
| <a name="SETUP_SLACK_MARGIN"></a>SETUP_SLACK_MARGIN| Specifies a time margin for the slack when fixing setup violations.| |
| <a name="SET_RC_TCL"></a>SET_RC_TCL| Metal & Via RC definition file path.| |
Expand All @@ -160,7 +164,8 @@ configuration file.
| <a name="VERILOG_FILES"></a>VERILOG_FILES| The path to the design Verilog files or JSON files providing a description of modules (check `yosys -h write_json` for more details).| |
| <a name="VERILOG_INCLUDE_DIRS"></a>VERILOG_INCLUDE_DIRS| Specifies the include directories for the Verilog input files.| |
| <a name="VERILOG_TOP_PARAMS"></a>VERILOG_TOP_PARAMS| Apply toplevel params (if exist).| |
## synth variables

## Synth variables

- [ABC_AREA](#ABC_AREA)
- [ABC_CLOCK_PERIOD_IN_PS](#ABC_CLOCK_PERIOD_IN_PS)
Expand All @@ -174,14 +179,16 @@ configuration file.
- [MIN_BUF_CELL_AND_PORTS](#MIN_BUF_CELL_AND_PORTS)
- [RESYNTH_AREA_RECOVER](#RESYNTH_AREA_RECOVER)
- [RESYNTH_TIMING_RECOVER](#RESYNTH_TIMING_RECOVER)
- [SDC_FILE](#SDC_FILE)
- [SDC_GUT](#SDC_GUT)
- [SYNTH_HIERARCHICAL](#SYNTH_HIERARCHICAL)
- [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
- [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT)
- [VERILOG_FILES](#VERILOG_FILES)
- [VERILOG_INCLUDE_DIRS](#VERILOG_INCLUDE_DIRS)
- [VERILOG_TOP_PARAMS](#VERILOG_TOP_PARAMS)

## floorplan variables
## Floorplan variables

- [ADDITIONAL_FILES](#ADDITIONAL_FILES)
- [CELL_PAD_IN_SITES_GLOBAL_PLACEMENT](#CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)
Expand All @@ -191,6 +198,7 @@ configuration file.
- [CORE_UTILIZATION](#CORE_UTILIZATION)
- [DIE_AREA](#DIE_AREA)
- [FLOORPLAN_DEF](#FLOORPLAN_DEF)
- [IO_CONSTRAINTS](#IO_CONSTRAINTS)
- [IO_PLACER_H](#IO_PLACER_H)
- [IO_PLACER_V](#IO_PLACER_V)
- [MACRO_BLOCKAGE_HALO](#MACRO_BLOCKAGE_HALO)
Expand All @@ -204,28 +212,34 @@ configuration file.
- [MAKE_TRACKS](#MAKE_TRACKS)
- [PDN_TCL](#PDN_TCL)
- [PLACE_DENSITY](#PLACE_DENSITY)
- [PLACE_PINS_ARGS](#PLACE_PINS_ARGS)
- [PLACE_SITE](#PLACE_SITE)
- [REMOVE_ABC_BUFFERS](#REMOVE_ABC_BUFFERS)
- [RTLMP_FLOW](#RTLMP_FLOW)
- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
- [TAPCELL_TCL](#TAPCELL_TCL)
- [TNS_END_PERCENT](#TNS_END_PERCENT)

## place variables
## Place variables

- [ADDITIONAL_FILES](#ADDITIONAL_FILES)
- [CELL_PAD_IN_SITES_DETAIL_PLACEMENT](#CELL_PAD_IN_SITES_DETAIL_PLACEMENT)
- [CELL_PAD_IN_SITES_GLOBAL_PLACEMENT](#CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)
- [GPL_ROUTABILITY_DRIVEN](#GPL_ROUTABILITY_DRIVEN)
- [GPL_TIMING_DRIVEN](#GPL_TIMING_DRIVEN)
- [IO_CONSTRAINTS](#IO_CONSTRAINTS)
- [IO_PLACER_H](#IO_PLACER_H)
- [IO_PLACER_V](#IO_PLACER_V)
- [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER)
- [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER)
- [PLACE_DENSITY](#PLACE_DENSITY)
- [PLACE_PINS_ARGS](#PLACE_PINS_ARGS)
- [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT)
- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
- [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
- [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT)

## cts variables
## Cts variables

- [ADDITIONAL_FILES](#ADDITIONAL_FILES)
- [CELL_PAD_IN_SITES_DETAIL_PLACEMENT](#CELL_PAD_IN_SITES_DETAIL_PLACEMENT)
Expand All @@ -239,31 +253,40 @@ configuration file.
- [POST_CTS_TCL](#POST_CTS_TCL)
- [REMOVE_CELLS_FOR_EQY](#REMOVE_CELLS_FOR_EQY)
- [SKIP_CTS_REPAIR_TIMING](#SKIP_CTS_REPAIR_TIMING)
- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
- [TNS_END_PERCENT](#TNS_END_PERCENT)

## grt variables
## Grt variables

- [ADDITIONAL_FILES](#ADDITIONAL_FILES)
- [CELL_PAD_IN_SITES_DETAIL_PLACEMENT](#CELL_PAD_IN_SITES_DETAIL_PLACEMENT)
- [DETAILED_METRICS](#DETAILED_METRICS)
- [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER)
- [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER)
- [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT)
- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
- [TNS_END_PERCENT](#TNS_END_PERCENT)

## route variables
## Route variables

- [ADDITIONAL_FILES](#ADDITIONAL_FILES)
- [DETAILED_ROUTE_ARGS](#DETAILED_ROUTE_ARGS)
- [DETAILED_ROUTE_END_ITERATION](#DETAILED_ROUTE_END_ITERATION)
- [FILL_CELLS](#FILL_CELLS)
- [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER)
- [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER)
- [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT)
- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)

## final variables
## Final variables

- [ADDITIONAL_FILES](#ADDITIONAL_FILES)
- [GND_NETS_VOLTAGES](#GND_NETS_VOLTAGES)
- [MAX_ROUTING_LAYER](#MAX_ROUTING_LAYER)
- [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER)
- [PWR_NETS_VOLTAGES](#PWR_NETS_VOLTAGES)
- [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT)
- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)

## All stages variables

Expand All @@ -286,12 +309,10 @@ configuration file.
- [DPO_MAX_DISPLACEMENT](#DPO_MAX_DISPLACEMENT)
- [ENABLE_DPO](#ENABLE_DPO)
- [FASTROUTE_TCL](#FASTROUTE_TCL)
- [FILL_CELLS](#FILL_CELLS)
- [FILL_CONFIG](#FILL_CONFIG)
- [GDS_FILES](#GDS_FILES)
- [GENERATE_ARTIFACTS_ON_FAILURE](#GENERATE_ARTIFACTS_ON_FAILURE)
- [GLOBAL_PLACEMENT_ARGS](#GLOBAL_PLACEMENT_ARGS)
- [GND_NETS_VOLTAGES](#GND_NETS_VOLTAGES)
- [GUI_TIMING](#GUI_TIMING)
- [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN)
- [IR_DROP_LAYER](#IR_DROP_LAYER)
Expand All @@ -302,19 +323,16 @@ configuration file.
- [PLATFORM](#PLATFORM)
- [PRESERVE_CELLS](#PRESERVE_CELLS)
- [PROCESS](#PROCESS)
- [PWR_NETS_VOLTAGES](#PWR_NETS_VOLTAGES)
- [RCX_RULES](#RCX_RULES)
- [RECOVER_POWER](#RECOVER_POWER)
- [REPAIR_PDN_VIA_LAYER](#REPAIR_PDN_VIA_LAYER)
- [SC_LEF](#SC_LEF)
- [SDC_FILE](#SDC_FILE)
- [SEAL_GDS](#SEAL_GDS)
- [SETUP_SLACK_MARGIN](#SETUP_SLACK_MARGIN)
- [SET_RC_TCL](#SET_RC_TCL)
- [SKIP_GATE_CLONING](#SKIP_GATE_CLONING)
- [SKIP_INCREMENTAL_REPAIR](#SKIP_INCREMENTAL_REPAIR)
- [SKIP_PIN_SWAP](#SKIP_PIN_SWAP)
- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
- [SLEW_MARGIN](#SLEW_MARGIN)
- [SYNTH_ARGS](#SYNTH_ARGS)
- [TAP_CELL_NAME](#TAP_CELL_NAME)
Expand Down
152 changes: 83 additions & 69 deletions flow/scripts/generate-variables-docs.py
Original file line number Diff line number Diff line change
@@ -1,83 +1,97 @@
#!/usr/bin/env python3
# variables.yaml is the single source of truth w.r.t. metainformation about
# the ORFS variables.
#
# This script injects an autogenerated section in FlowVariables.md with
# information about the variables from variables.yaml.
"""
This script injects an autogenerated section in FlowVariables.md with
information about the variables from variables.yaml.
variables.yaml is the single source of truth w.r.t. metainformation about
the ORFS variables.
"""
import os
import yaml

dir_path = os.path.dirname(os.path.realpath(__file__))

yaml_path = os.path.join(dir_path, "variables.yaml")
preferred_order = ["synth", "floorplan", "place", "cts", "grt", "route", "final"]
table_header = "| Variable | Description | Default |\n| --- | --- | --- |\n"

with open(yaml_path, "r") as file:
data = yaml.safe_load(file)

preferred_order = ["synth", "floorplan", "place", "cts", "grt", "route", "final"]
stages = {stage for value in data.values() for stage in value.get("stages", [])}
# convert set of stages to stages in a list in the preferred order, but
# list all stages
stages = [stage for stage in preferred_order if stage in stages] + [
stage for stage in stages if stage not in preferred_order
]
def load_yaml(yaml_path: str) -> dict:
if not os.path.exists(yaml_path):
raise FileNotFoundError(f"File {yaml_path} not found")
with open(yaml_path, "r") as file:
return yaml.safe_load(file)

markdown_table = ""

markdown_table += "## Variables in alphabetic order\n\n"
table_header = "| Variable | Description | Default |\n| --- | --- | --- |\n"
table_rows = ""
for key in sorted(data):
value = data[key]
description = value.get("description", "").replace("\n", " ").strip()
table_rows += (
def preprocess(data: dict) -> list:
# convert set of stages to stages in a list in the preferred order, but
# list all stages
stages = {stage for value in data.values() for stage in value.get("stages", [])}
stages = [stage for stage in preferred_order if stage in stages] + [
stage for stage in stages if stage not in preferred_order
]
return stages


def generate_md(data: dict, stages: list) -> None:
# Populate overview section
markdown_table = "## Variables in alphabetic order\n\n"
table_rows = "\n".join(
f'| <a name="{key}"></a>{key}'
+ f"| {description}"
+ f'| {value.get("default", "")} |\n'
+ f"| {value.get('description', '').replace('\n', ' ').strip()}"
+ f'| {value.get("default", "")} |'
for key, value in sorted(data.items())
)
markdown_table += table_header + table_rows + "\n\n"

markdown_table += table_header + table_rows

for stage in stages + ["All stages", "Uncategorized"]:
markdown_table += f"## {stage} variables\n\n"
stage_keys = [
key
for key in sorted(data)
if (
("stages" in data[key] and stage in data[key]["stages"])
or ("stages" not in data[key] and stage == "Uncategorized")
or (
stage == "All stages"
and set(data[key].get("stages", [])) == set(stages)
# Populate stages section
for stage in stages + ["All stages", "Uncategorized"]:
markdown_table += f"## {stage.capitalize()} variables\n\n"
stage_keys = [
key
for key in sorted(data)
if (
("stages" in data[key] and stage in data[key]["stages"])
or ("stages" not in data[key] and stage == "Uncategorized")
or (
stage == "All stages"
and set(data[key].get("stages", [])) == set(stages)
)
)
)
]
markdown_table += "\n".join(map(lambda k: f"- [{k}](#{k})", stage_keys))
markdown_table += "\n\n"

docs = os.path.join(dir_path, "..", "..", "docs", "user", "FlowVariables.md")
with open(docs, "r") as file:
lines = file.readlines()

# Find the section to replace
start_marker = "# Automatically generated"
end_marker = "# "
start_index = None
end_index = len(lines)

for i, line in enumerate(lines):
if line.startswith(start_marker):
start_index = i + 1
elif start_index is not None and line.startswith(end_marker):
end_index = i
break

if start_index is None:
raise ValueError("Start marker not found")

# Replace the section with the new table
new_lines = lines[:start_index] + [markdown_table] + lines[end_index:]

# Write the updated content back to FlowVariables.md
with open(docs, "w") as file:
file.writelines(new_lines)
]
markdown_table += "\n".join(map(lambda k: f"- [{k}](#{k})", stage_keys))
markdown_table += "\n\n"

# Read the existing content of FlowVariables.md
docs = os.path.join(dir_path, "..", "..", "docs", "user", "FlowVariables.md")
with open(docs, "r") as file:
lines = file.readlines()

# Find the section to replace
start_marker = "# Automatically generated"
end_marker = "# "
start_index = None
end_index = len(lines)

for i, line in enumerate(lines):
if line.startswith(start_marker):
start_index = i + 1
elif start_index is not None and line.startswith(end_marker):
end_index = i
break

if start_index is None:
raise ValueError("Start marker not found")

# Replace the section with the new table
new_lines = lines[:start_index] + [markdown_table] + lines[end_index:]

# Write the updated content back to FlowVariables.md
with open(docs, "w") as file:
file.writelines(new_lines)


if __name__ == "__main__":
data = load_yaml(yaml_path)
stages = preprocess(data)
generate_md(data, stages)
print("FlowVariables.md updated successfully")
15 changes: 15 additions & 0 deletions flow/scripts/tunable.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,15 @@
#!/usr/bin/env python3

import os
import yaml

dir_path = os.path.dirname(os.path.realpath(__file__))

yaml_path = os.path.join(dir_path, "variables.yaml")
with open(yaml_path, "r") as file:
data = yaml.safe_load(file)

for key, value in data.items():
if value.get("tunable", False) is False:
continue
print(f"{key}")
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