Privileged instructions can't trigger Trace exceptions

CHANGELOG.md

@@ -16,8 +16,6 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - CPU behavior is now controlled using a trait and generic member instead of features (breaking).
 - Move the register access helper methods to the Registers struct.
 - Status Register's default function returns a SR with value 0x2700 (breaking).
-- Interrupt's exception processing sets the interrupt priority mask.
-- Interrupt level 7 is non-maskable.
 - Use wrapping types and methods so overflow checks can be enabled.
 - Make MemoryIter generic over the underlying MemoryAccess trait object.
 
@@ -30,6 +28,9 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Fix immediate Shift/Rotate count of 0 not disassembled as 8.
 - Fix ABCD/NBCD/SBCD.
 - Fix DIVS/DIVU changing the destination even when an overflow occured.
+- Interrupt's exception processing sets the interrupt priority mask.
+- Interrupt level 7 is non-maskable.
+- Privileged instructions can't trigger Trace exceptions.
 
 ## [0.1.1] - 2022-08-28
 ### Fixed

m68000/src/interpreter_disassembler.rs

@@ -64,7 +64,7 @@ impl<CPU: CpuDetails> M68000<CPU> {
  let exception = match Execute::<CPU, M>::EXECUTE[isa as usize](self, memory, &instruction) {
  Ok(cycles) => {
  cycle_count += cycles;
- if trace {
+ if trace && !isa.is_privileged() {
  Some(Vector::Trace as u8)
  } else {
  None

m68000/src/interpreter_fast.rs

@@ -113,7 +113,7 @@ impl<CPU: CpuDetails> M68000<CPU> {
  let exception = match Execute::<CPU, M>::EXECUTE[isa as usize](self, memory) {
  Ok(cycles) => {
  cycle_count += cycles;
- if trace {
+ if trace && !isa.is_privileged() {
  Some(Vector::Trace as u8)
  } else {
  None

m68000/src/isa.rs

@@ -101,6 +101,22 @@ pub enum Isa {
  _Size,
 }
 
+impl Isa {
+ pub const fn is_privileged(self) -> bool {
+ match self {
+ Self::Andisr => true,
+ Self::Eorisr => true,
+ Self::Movesr => true,
+ Self::Moveusp => true,
+ Self::Orisr => true,
+ Self::Reset => true,
+ Self::Rte => true,
+ Self::Stop => true,
+ _ => false,
+ }
+ }
+}
+
 impl From<u16> for Isa {
  /// Returns the instruction represented by the given opcode.
  fn from(opcode: u16) -> Self {