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A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)

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SnrNotHere16/FPGADivisionFloatingPoint

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FPGA Floating Point Division (Single Precision)

Simple project using the floating point division IP Core's division functionality from Xilinx
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NEXYS 4 DDR (Artix-7)

Block Diagram for Programming Logic System. Project: https://github.com/SnrNotHere16/FPGADivisionFloatingPoint/tree/main/FloatingPointDivisionNexys4DDR/FPFPGA/Division alt text 0/0 = 7FC0_0000 = NaN alt text alt text -2/0 = FF80_0000 = -inf alt text alt text 2/0 = 7F80_0000 = inf alt text alt text 0/-2 = 8000_0000 = -0 alt text alt text
0/2 = 0000_0000 = 0
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ZYBO Z7 ZYNQ-7020

Block Diagram for Programming Logic System. Project: https://github.com/SnrNotHere16/FPGADivisionFloatingPoint/tree/main/FPDivZYBO/Project/FloatingDivisionZybo
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A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)

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c sdk fpga zynq verilog xilinx floating-point hdl division xilinx-vivado microblaze zynq-7000 nexys4ddr floating-ip artix-7 floating-point-conversion

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