Pinned Loading

1. -32-bit-Brent-Kung-Logarithmic-Adder-Circuit-using-VHDL -32-bit-Brent-Kung-Logarithmic-Adder-Circuit-using-VHDL Public

2. -Calculation-of-parasitic-delay-and-transistor-width-ratio -Calculation-of-parasitic-delay-and-transistor-width-ratio Public

3. Design-and-Implementation-of-Dual-Clock-Asynchronous-FIFO Design-and-Implementation-of-Dual-Clock-Asynchronous-FIFO Public

   Dual Clock Asynchronous FIFO with synchronizers

   Verilog

4. Design-and-Implementation-of-Hardware-Communication-Protocols Design-and-Implementation-of-Hardware-Communication-Protocols Public

   UART, SPI

   Verilog

5. RTL-to-GDS-flow-of-MIPS-Processor-using-Opensource-Tools- RTL-to-GDS-flow-of-MIPS-Processor-using-Opensource-Tools- Public

   Tools used: Yosys, OpenSTA, OpenROAD

   Verilog

6. Verification-of-Sequential-Circuit-using-SAT-Solver Verification-of-Sequential-Circuit-using-SAT-Solver Public

   MiniSAT, C++

   Shell