boards/samd5x: GCLK source for ADC must not exceed 100 MHz

[benpicco]

Contribution description

When not otherwise specified, the ADC will be clocked by GCLK_MAIN which in case of SAM D5x/E5x is configured to run at 120 MHz.

This exceeds the maximum allowed input GCLK frequency.

We could use DIV4 here as well, but as long as we don't have the sample length calculation in, better run the ADC at a more conservative pace.

Testing procedure

tests/periph/adc still works

2024-10-22 13:24:57,458 # main(): This is RIOT! (Version: 2024.10-devel-340-gdf7e3-boards/samd5x-adc_freq)
2024-10-22 13:24:57,458 # 
2024-10-22 13:24:57,461 # RIOT ADC peripheral driver test
2024-10-22 13:24:57,461 # 
2024-10-22 13:24:57,467 # This test will sample all available ADC lines once every 100ms with
2024-10-22 13:24:57,472 # a 10-bit resolution and print the sampled results to STDIO
2024-10-22 13:24:57,472 # 
2024-10-22 13:24:57,473 # 
2024-10-22 13:24:57,475 # Successfully initialized ADC_LINE(0)
2024-10-22 13:24:57,478 # Successfully initialized ADC_LINE(1)
2024-10-22 13:24:57,482 # Successfully initialized ADC_LINE(2)
2024-10-22 13:24:57,483 # ADC_LINE(0): 209
2024-10-22 13:24:57,485 # ADC_LINE(1): 215
2024-10-22 13:24:57,486 # ADC_LINE(2): 211
2024-10-22 13:24:57,588 # ADC_LINE(0): 194
2024-10-22 13:24:57,589 # ADC_LINE(1): 133
2024-10-22 13:24:57,591 # ADC_LINE(2): 204

Issues/PRs references

[riot-ci]

Murdock results

✔️ PASSED

419fc6e boards/samd5x: GCLK source for ADC must not exceed 100 MHz

Success	Failures	Total	Runtime
2251	0	2251	06m:43s

Artifacts

• Documentation preview

[dylad]

LGTM.
doccheck is complaining. Feels free to squash right away.