This repository compares RISC-V soft cores in order to help you choose the best one for your application. There are so many of these soft cores, it is very hard to choose the right one. There is a curated List of important RISC-V cores, but it is not current, categorized, nor opinionatied. Some are good for education, some for error checking, some for size, some for speed, some for a particular FPGA architecture, some for name recognition. This repository should help you sort through the noise and choose the best one for your needs.
This document will soon cover a vast amount of code. If there are any mistakes, please forgive me and create an issue or make a pull request.
These are two cores that have a data path smaller than 32 bits wide, 1, 2, 4, or 8 bits wide. That allows them to be much smaller, but then they take a lot more clock cycles to execute an instruction. This is where my interest and expertise lie.
The Serve soft core has a 1 bit wide data path, only requires 198 ICE40 LUTs, but takes a lot of clock cycles (how many?) to execute each instruction.
Video FaxyRV has a scalable data path to 1, 2, 4, or 8 bits with many variants.
A bit serial processor, where the registers rotate. On every clock cycle it accesses one 32 bit memory word, where each bit is from a different register. Memory is FerroElectric RAM (FRAM), like Flash, but can be written to 10,000,000,000,000 times.
This section compares RISC-V soft cores which can run on the less expensive, more popular Lattice ICE40 UP5K FPGA.
This is a great cpu for learning verilog. Starting with a blinky, the system goes through 20 metamorphosii and becomes a RISC-V chip. The creator Bruno Levy is this charming professorial type, and his hench man Matthia Koch is a brilliant technologist. @BrunoLevy @Mecrisp
A platform independent VHDL processor with an emphasis on error-checking.
Special focus is paid on execution safety to provide defined and predictable behavior at any time. For example, the CPU ensures all memory accesses are properly acknowledged and all invalid/malformed instructions are always detected as such. Whenever an unexpected state occurs the application software is informed via precise and resumable hardware exceptions.
Video This is a very configurable CPU written in its own langauge SpinalHDL whitten in Scala. it is perfect for pipelined CPUs. You can edit code in one file which affects different parts of the pipeline. Don't even think of trying to do that in Verilog or VHDL. Of course there is a huge learning curve here. Scala and SpinalHDL are both quite large. Like the author says, do not start by reading the code of an expert SpinalHDL developers, start with the much simpler tutorials, and slowly build up to understanding more complex ideas.
Getting your organization to accept SpinalHDL is a huge challenge. But building complex configurable pipelined CPUs in Verilog is a bigger challenge.
These cpus have to cores which share an ALU and control structures. On calls and jumps usually RISC-V computation pauses while the core loads thenext instruction and decodesit. By alternatiing between the two cores, this problem is avoided. And many applications can easily be split into twothreads sharing the same memory. By @[email protected]
Here are the larger portable soft cores, ones which cannot run on an ICE40 board.
This is the soft core created by the open source Yosys synthesizer team. ""It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt controller.
There are a number of RISC-V cores built in languages other than Verilog, or VHDL. Here are some notable ones worth mentioning.
This is an award winning soft core, with great demos, listed above. Getting your organization to accept SpinalHDL is a huge challenge. But building complex configurable pipelined CPUs in Verilog is a bigger challenge.
PipelineC is a very accessible way to program FPGAs. Whle Verilog is very hard to learn, data flow using a functional programming approach in C is very understandable for the beginner. Slides @PipelineC
Clash is an HDL written in Haskell, a functional programmign language. Like the author said, functional programming is very inefficient, but it is a great way to model digital circuits. There is no way anyyone could know all of the different hardware HDLs, but this one appeals to me the most. I could be wrong. Of course getting your organization to approve Haskell could be a hard sell.
Most of the FPGA vendors provide RISC-V soft cores optimised for their platform. They will be listed here. so this section will really be a comparison between (board+Soft core) from each of the vendors.
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AMD/Xilinx MicroBlaze V
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Altera NIOS
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Microchip**, Mi-V RV32 Soft RISC-V Processor
Contributions are welcome. What do you want added? Please get off of corporate social media, and message me @PythonLinkson open-source, propaganda and censoreship free Discord. For longer discussions, please visit the FPGA Discord Server, RISC-V channel and mention "@Christopher Lozinski".
The author does not produce, support nor endorse any specific RISC-V cores. He does not accept financial inducements from any of the RISC-V core vendors. Instead he wants everyone to port their RISC-V cores to the pico-ice circuit board, and buy many $35 pico-ice boards. At some point I will also talk about very small stack machines here.
There are a number of other RISC-v soft core lists. Two are 5 years old. One is 3 years old. One if based on vendor submissions, rather than editorial reviews. One includes hard cores. Surprising that no one else has created a list like this.