Advanced-Logic-Design

Code developed for the labs of the second year's undergraduate course Advanced Logic Design of the Electrical and Computer Engineering school at Technical University of Crete. This project was a team work shared with my colleague Tzanis Fotakis.

In the "Help Docs" folder there are some getting started documents for using VHDL language, Xilinx ISE an the Basys2 board. Each lab folder contains an Exercise pdf, a Report pdf and also one or more folders named accordingly to the circuit they contain. Each such folder contains all the needed .vhd files to create the project.

All code was developed using Xilinx ISE.

To view the working code and the simulations:

1. Create an empty Xilinx ISE VHDL93 project
2. Add all the .vhd files in the project using the "Add sources" button.
3. Press Simulate design