This is a simple pipelined processor that serves as the project for the Computer Architecture course (CMP 3010) taught at Cairo University.
NOP
HLT
SETC
NOT Rdst
INC Rdst
OUT Rdst
IN Rdst
MOV Rsrc, Rdst
ADD Rdst, Rsrc1, Rsrc2
SUB Rdst, Rsrc1, Rsrc2
AND Rdst, Rsrc1, Rsrc2
IADD Rdst, Rsrc2 ,Imm
PUSH Rdst
POP Rdst
LDM Rdst, Imm
LDD Rdst, offset(Rsrc)
STD Rsrc1, offset(Rsrc2)
JZ Rdst
JN Rdst
JC Rdst
JMP Rdst
- Data forwarding is missing
- Two types of Exceptions are implemented (one related to stack memory and the other to data memory)
Gheiath Ajam |
Ahmed Sayed |
Yousef El Shabrawy |