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simulation: pci_control testbench
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    there is still a bug in the EZ_USB chip simulation. It stalls whenever the wr-core sends
    the first character over UART interface to the EZ_USB chip
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Michael Reese committed Aug 31, 2023
1 parent e4f18a1 commit 88c7de5
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Showing 38 changed files with 47,218 additions and 8 deletions.
2 changes: 1 addition & 1 deletion modules/dm_diag/dm_diag.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -260,7 +260,7 @@ begin
begin
if rising_edge(clk_ref_i) then
if(rst_ref_n_i = '0' OR s_ctrl_reset_o(0) = '1' OR s_deadtime_stop = '1') then
r_deadtime <= "0" & to_unsigned(-1, r_deadtime'length-1);
r_deadtime <= ('0', others => '1');--"0" & to_unsigned(-1, r_deadtime'length-1);
r_deadtime_run <= "0";
else
r_deadtime_run(0) <= (r_deadtime_run(0) OR s_deadtime_start);
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Original file line number Diff line number Diff line change
Expand Up @@ -627,9 +627,10 @@ gen_clock_sync_yes : if (g_with_sync = true) generate
ld_hi_p0(channel_count) <= '1';
else
ld_lo_p0(channel_count) <= '1';
channel_count <= channel_count + 1;
if (channel_count = g_num_outputs-1) then
channel_count <= 0;
else
channel_count <= channel_count + 1;
end if;
end if;
set_lo_count <= set_lo_count xor '1';
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8 changes: 5 additions & 3 deletions modules/monster/monster.vhd
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Expand Up @@ -77,6 +77,7 @@ entity monster is
g_family : string; -- "Arria II", "Arria V", or "Arria 10"
g_project : string;
g_flash_bits : natural;
g_simulation : boolean; -- false for synthesis, true for simulation
g_psram_bits : natural;
g_ram_size : natural;
g_gpio_inout : natural;
Expand Down Expand Up @@ -977,8 +978,8 @@ begin
generic map(
g_plls => 4,
g_clocks => 4,
g_areset => f_pick(c_is_arria5, 100, 1)*1024,
g_stable => f_pick(c_is_arria5, 100, 1)*1024)
g_areset => f_pick(g_simulation, 16, f_pick(c_is_arria5, 100, 1)*1024),
g_stable => f_pick(g_simulation, 16, f_pick(c_is_arria5, 100, 1)*1024))
port map(
clk_free_i => clk_free,
rstn_i => core_rstn_i,
Expand Down Expand Up @@ -1577,7 +1578,8 @@ end generate;
usb_fd_io <= s_usb_fd_o when s_usb_fd_oen='1' else (others => 'Z');
usb : ez_usb
generic map(
g_sdb_address => c_top_sdb_address)
g_sdb_address => c_top_sdb_address,
g_sys_freq => f_pick(g_simulation, 10, 65000)) -- this is 65000 kHz for g_simulation=false, and 10 kHz for g_simulation=true
port map(
clk_sys_i => clk_sys,
rstn_i => rstn_sys,
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1 change: 1 addition & 0 deletions modules/monster/monster_pkg.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -80,6 +80,7 @@ package monster_pkg is

component monster is
generic(
g_simulation : boolean := false;
g_family : string; -- "Arria II" or "Arria V"
g_project : string;
g_flash_bits : natural;
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23 changes: 23 additions & 0 deletions testbench/tr_simulation/gsi_pexarria5/Manifest.py
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@@ -0,0 +1,23 @@
target = "altera"
action = "synthesis"

fetchto = "../../../ip_cores"
syn_tool = "quartus"
syn_device = "5agxma3d4f"
syn_grade = "i3"
syn_package = "27"
syn_top = "pci_control"
syn_project = "pci_control"

quartus_preflow = "pci_control.tcl"

files = [
"testbench.vhd",
]

modules = {
"local" : [
"../../../top/gsi_pexarria5/control",
]
}

284 changes: 284 additions & 0 deletions testbench/tr_simulation/gsi_pexarria5/build_id.mif
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@@ -0,0 +1,284 @@
-- Build ID Memory Initialization File
--
-- Project : scu_control
-- Platform : scu3 +comexpress
-- FPGA model : Arria II GX (ep2agx125ef29c5)
-- Source info : usb-poll-msi-2549
-- Build type : developer preview
-- Build date : Tue Apr 28 14:34:31 CEST 2020
-- Prepared by : Michael Reese <[email protected]>
-- Prepared on : belpc121
-- OS version : Arch Linux, kernel 5.4.8-arch1-1
-- Quartus : Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition
--
-- 11878658 ez-usb-msi: add usb msi in monster
-- a5272bcb beam_dump: test.sh -> typo
-- eef94812 Merge pull request #198 from GSI-CS-CO/enigma_beam_dump
-- 4546ddea Merge branch 'enigma' of https://github.com/GSI-CS-CO/bel_projects into enigma_beam_dump
-- 6049353b beam_dump: initial

DEPTH = 256;
WIDTH = 32;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;

CONTENT
BEGIN

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a9 : 00000000;
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ac : 00000000;
ad : 00000000;
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b0 : 00000000;
b1 : 00000000;
b2 : 00000000;
b3 : 00000000;
b4 : 00000000;
b5 : 00000000;
b6 : 00000000;
b7 : 00000000;
b8 : 00000000;
b9 : 00000000;
ba : 00000000;
bb : 00000000;
bc : 00000000;
bd : 00000000;
be : 00000000;
bf : 00000000;
c0 : 00000000;
c1 : 00000000;
c2 : 00000000;
c3 : 00000000;
c4 : 00000000;
c5 : 00000000;
c6 : 00000000;
c7 : 00000000;
c8 : 00000000;
c9 : 00000000;
ca : 00000000;
cb : 00000000;
cc : 00000000;
cd : 00000000;
ce : 00000000;
cf : 00000000;
d0 : 00000000;
d1 : 00000000;
d2 : 00000000;
d3 : 00000000;
d4 : 00000000;
d5 : 00000000;
d6 : 00000000;
d7 : 00000000;
d8 : 00000000;
d9 : 00000000;
da : 00000000;
db : 00000000;
dc : 00000000;
dd : 00000000;
de : 00000000;
df : 00000000;
e0 : 00000000;
e1 : 00000000;
e2 : 00000000;
e3 : 00000000;
e4 : 00000000;
e5 : 00000000;
e6 : 00000000;
e7 : 00000000;
e8 : 00000000;
e9 : 00000000;
ea : 00000000;
eb : 00000000;
ec : 00000000;
ed : 00000000;
ee : 00000000;
ef : 00000000;
f0 : 00000000;
f1 : 00000000;
f2 : 00000000;
f3 : 00000000;
f4 : 00000000;
f5 : 00000000;
f6 : 00000000;
f7 : 00000000;
f8 : 00000000;
f9 : 00000000;
fa : 00000000;
fb : 00000000;
fc : 00000000;
fd : 00000000;
fe : 00000000;
ff : 00000000;
END;
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