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there is still a bug in the EZ_USB chip simulation. It stalls whenever the wr-core sends the first character over UART interface to the EZ_USB chip
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Michael Reese
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Aug 31, 2023
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Submodule saftlib
updated
8 files
+1 −26 | .github/workflows/main.yml | |
+1 −1 | README.md | |
+1 −1 | configure.ac | |
+2 −2 | examples/SimpleFirmware/Makefile.am | |
+1 −1 | saftbus/examples/ex00/Makefile.am | |
+2 −8 | saftbus/examples/ex01_simple_dice/Makefile.am | |
+2 −20 | saftbus/examples/ex02_dice_cup/Makefile.am | |
+2 −3 | src/saft-ctl.cpp |
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target = "altera" | ||
action = "synthesis" | ||
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fetchto = "../../../ip_cores" | ||
syn_tool = "quartus" | ||
syn_device = "5agxma3d4f" | ||
syn_grade = "i3" | ||
syn_package = "27" | ||
syn_top = "pci_control" | ||
syn_project = "pci_control" | ||
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quartus_preflow = "pci_control.tcl" | ||
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files = [ | ||
"testbench.vhd", | ||
] | ||
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modules = { | ||
"local" : [ | ||
"../../../top/gsi_pexarria5/control", | ||
] | ||
} | ||
|
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-- Build ID Memory Initialization File | ||
-- | ||
-- Project : scu_control | ||
-- Platform : scu3 +comexpress | ||
-- FPGA model : Arria II GX (ep2agx125ef29c5) | ||
-- Source info : usb-poll-msi-2549 | ||
-- Build type : developer preview | ||
-- Build date : Tue Apr 28 14:34:31 CEST 2020 | ||
-- Prepared by : Michael Reese <[email protected]> | ||
-- Prepared on : belpc121 | ||
-- OS version : Arch Linux, kernel 5.4.8-arch1-1 | ||
-- Quartus : Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition | ||
-- | ||
-- 11878658 ez-usb-msi: add usb msi in monster | ||
-- a5272bcb beam_dump: test.sh -> typo | ||
-- eef94812 Merge pull request #198 from GSI-CS-CO/enigma_beam_dump | ||
-- 4546ddea Merge branch 'enigma' of https://github.com/GSI-CS-CO/bel_projects into enigma_beam_dump | ||
-- 6049353b beam_dump: initial | ||
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DEPTH = 256; | ||
WIDTH = 32; | ||
ADDRESS_RADIX = HEX; | ||
DATA_RADIX = HEX; | ||
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CONTENT | ||
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END; |
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