Wishlist: proposed features

General ideas (To be studied, classified and prioritized)

Moved to 0.2.1

• Execute Icestudio as a client, on a remote server. Instead of "apio build" execute "192.168.0.1 / apio build"

Moved to 0.2.2

• Generation of test-benches (export generic testbenches) (proposed by Carlos Santiago Díaz)

Moved to 0.2.3

• Standalone packaging
• Show examples for the selected board
• Add boards documentation
• Detect system language (https://github.com/Elzair/node-lang-info) (Proposed by Salvador)
• Option for Showing the Resources availables / used when synthetising a circuit (It will be necessary to parse the output generated by Arachne)
• Close error notifications only on click (Proposed by AlexTC)
• View selected board in the panel (Proposed by AlexTC)
• Manage the wires that are connected, placing a dot en the union. Sometimes is hard to visualize if two wires that cross are or not connected (Proposed by Jose Javier Jimenez Viton)

Moved to 0.2.4

• Block-code with user-defined parameters (Ex. number of bits of the divisor). When the block is placed, also the parameter can be set
• Use Constant blocks for parameters (Proposed by Salvador)
• Use N-bit wires
• When exporting a block, the ordination or the outputs should be taken from the y-coordinate. Now it is taken from the ordination of creation of the pin. It is more clear if the ordination is taken from the original block
• Tooltip with a block description (Proposed by Carlos Santiago Díaz)
• Add boards photos information (Proposed by Salvador)
• Notification: save current project before new project.
• Detect project modifications.

Wishlist

• Simulation with GTKwave (Proposed by Carlos Santiago Díaz)
• Serial terminal integrated in Icestudio
• Generation of Finite state machines (Proposed by Carlos Santiago Díaz)
• Test with Electron
• Parametrized blocks
• Iterative block edition
• Refactor all graphics: jointjs has behavior problems with SVG, HTML elements, Mouse events and zIndexes.
• Import modules with write access. Currently, when a module is imported into a project, you can only see the code, but cannot change anything. After using icestudio with real project, I think (obijuan) that it would be better if the modules can be changed inside the project. I really do not know if this is easy or hard to implement. The changes should only happen in the module edited. If there are many instances of a module, only the one instance is changed
• Option for update the modules. If you want to include a new updated version of a module, which have many instances in the current project, it would be great to have an option for doing that (all the modules updated)
• Multimodule block code. It is a verilog block, similar to the 0.2 block code, but more modules can be put inside. Only the top-level module will be available from icestudio. This feature will let us to re-use all the current opensource cores available in verilog. Without any modification, all these cores can be used in icestudio (just copying and pasting the verilog modules). For example, the simplez educational processor, can be embebed into a block, only with the needed pins: rst, clk, ports.. just like using a standar microcontroller, but in icestudio. Without having to change the verilog code (or reimplementing every module in icestudio) (Proposed by Obijuan)
• Blocks/Examples/Templates manager from GitHub.
• Edit FPGA I/O pin by number (Proposed by Democrito)
• Colored wires (Proposed by Democrito)
• Undo/Redo (Proposed by AlexTC)
• Add labels to wires (Proposed by tonicobi)