Fix format and stuff

DynamoRIO · Mar 27, 2024 · 3fde8ca · 3fde8ca
1 parent e1312d9
commit 3fde8ca
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Showing 2 changed files with 5 additions and 1 deletion.
diff --git a/core/lib/instrument.c b/core/lib/instrument.c
@@ -6516,8 +6516,10 @@ dr_get_mcontext_priv(dcontext_t *dcontext, dr_mcontext_t *dmc, priv_mcontext_t *
         } else {
             set_stolen_reg_val(dr_mcontext_as_priv_mcontext(dmc),
                                (reg_t)d_r_get_tls(os_tls_offset(TLS_REG_STOLEN_SLOT)));
+#    ifdef RISCV64
             set_tp_reg_val(dr_mcontext_as_priv_mcontext(dmc),
                            (reg_t)os_get_app_tls_base(dcontext, TLS_REG_LIB));
+#    endif
         }
     }
 #endif
@@ -6594,7 +6596,9 @@ dr_set_mcontext(void *drcontext, dr_mcontext_t *context)
     if (TEST(DR_MC_INTEGER, context->flags)) {
         /* restore the reg val on the stack clobbered by the copy above */
         set_stolen_reg_val(state, stolen_reg_val);
+#    ifdef RISCV64
         set_tp_reg_val(state, tp_reg_val);
+#    endif
     }
 #endif
 

diff --git a/core/unix/os.c b/core/unix/os.c
@@ -1783,7 +1783,7 @@ os_timeout(int time_in_milliseconds)
             __asm__ __volatile__("ld %0, %1(tp) \n\t"                   \
                                  "add %0, %0, %2 \n\t"                  \
                                  "ld %0, 0(%0) \n\t"                    \
-                                 : "+r"(var)                           \
+                                 : "+r"(var)                            \
                                  : "i"(DR_TLS_BASE_OFFSET), "r"(offs)); \
         } while (0)
 #endif /* X86/ARM/RISCV64 */