move docs

CQCL · Oct 22, 2024 · e7f61fc · e7f61fc
1 parent caa8aca
commit e7f61fc
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/hugr-passes/src/dataflow/datalog.rs b/hugr-passes/src/dataflow/datalog.rs
@@ -15,8 +15,7 @@ type PV<V> = PartialValue<V>;
 /// Basic structure for performing an analysis. Usage:
 /// 1. Get a new instance via [Self::default()]
 /// 2. (Optionally / for tests) zero or more [Self::prepopulate_wire] with initial values
-/// 3. Call [Self::run] to produce [AnalysisResults] which can be inspected via
-/// [read_out_wire](AnalysisResults::read_out_wire)
+/// 3. Call [Self::run] to produce [AnalysisResults]
 pub struct Machine<V: AbstractValue>(Vec<(Node, IncomingPort, PartialValue<V>)>);
 
 /// derived-Default requires the context to be Defaultable, which is unnecessary

diff --git a/hugr-passes/src/dataflow/results.rs b/hugr-passes/src/dataflow/results.rs
@@ -4,7 +4,8 @@ use hugr_core::{ops::Value, types::ConstTypeError, HugrView, IncomingPort, Node,
 
 use super::{AbstractValue, PartialValue};
 
-/// Results of a dataflow analysis, packaged with context for easy inspection
+/// Results of a dataflow analysis, packaged with the Hugr for easy inspection.
+/// Methods allow inspection, specifically [read_out_wire](Self::read_out_wire).
 pub struct AnalysisResults<V: AbstractValue, H: HugrView> {
  pub(super) hugr: H,
  pub(super) in_wire_value: Vec<(Node, IncomingPort, PartialValue<V>)>,