Merge remote-tracking branch 'origin/main' into refactor/rewrites_use…

…_hugrmut_meths

src/builder.rs

@@ -17,8 +17,8 @@ pub use build_traits::{
 mod dataflow;
 pub use dataflow::{DFGBuilder, DFGWrapper, FunctionBuilder};
 
-mod module_builder;
-pub use module_builder::ModuleBuilder;
+mod module;
+pub use module::ModuleBuilder;
 
 mod cfg;
 pub use cfg::{BlockBuilder, CFGBuilder};
@@ -29,8 +29,8 @@ pub use tail_loop::TailLoopBuilder;
 mod conditional;
 pub use conditional::{CaseBuilder, ConditionalBuilder};
 
-mod circuit_builder;
-pub use circuit_builder::{AppendWire, CircuitBuilder};
+mod circuit;
+pub use circuit::CircuitBuilder;
 
 #[derive(Debug, Clone, PartialEq, Eq, Error)]
 /// Error while building the HUGR.
@@ -66,7 +66,7 @@ pub enum BuildError {
 
  /// Error in CircuitBuilder
  #[error("Error in CircuitBuilder: {0}.")]
- CircuitError(#[from] circuit_builder::CircuitBuildError),
+ CircuitError(#[from] circuit::CircuitBuildError),
 }
 
 #[cfg(test)]

src/builder/circuit_builder.rs → src/builder/circuit.rs

@@ -2,6 +2,7 @@ use std::collections::HashMap;
 
 use thiserror::Error;
 
+use crate::hugr::CircuitUnit;
 use crate::ops::OpType;
 
 use super::{BuildError, Dataflow};
@@ -16,28 +17,6 @@ pub struct CircuitBuilder<'a, T: ?Sized> {
  builder: &'a mut T,
 }
 
-/// Enum for specifying a [`CircuitBuilder`] input wire using either an index to
-/// the builder vector of wires, or an arbitrary other wire.
-#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
-pub enum AppendWire {
- /// Arbitrary input wire.
- W(Wire),
- /// Index to CircuitBuilder vector of wires.
- I(usize),
-}
-
-impl From<usize> for AppendWire {
- fn from(value: usize) -> Self {
- AppendWire::I(value)
- }
-}
-
-impl From<Wire> for AppendWire {
- fn from(value: Wire) -> Self {
- AppendWire::W(value)
- }
-}
-
 #[derive(Debug, Clone, PartialEq, Eq, Error)]
 /// Error in [`CircuitBuilder`]
 pub enum CircuitBuildError {
@@ -76,7 +55,7 @@ impl<'a, T: Dataflow + ?Sized> CircuitBuilder<'a, T> {
  #[inline]
  /// The same as [`CircuitBuilder::append_with_outputs`] except it assumes no outputs and
  /// instead returns a reference to self to allow chaining.
- pub fn append_and_consume<A: Into<AppendWire>>(
+ pub fn append_and_consume<A: Into<CircuitUnit>>(
  &mut self,
  op: impl Into<OpType>,
  inputs: impl IntoIterator<Item = A>,
@@ -87,15 +66,15 @@ impl<'a, T: Dataflow + ?Sized> CircuitBuilder<'a, T> {
  }
 
  /// Append an `op` with some inputs being the stored wires.
- /// Any inputs of the form [`AppendWire::I`] are used to index the
+ /// Any inputs of the form [`CircuitUnit::Linear`] are used to index the
  /// stored wires.
  /// The outputs at those indices are used to replace the stored wire.
  /// The remaining outputs are returned.
  ///
  /// # Errors
  ///
  /// This function will return an error if an index is invalid.
- pub fn append_with_outputs<A: Into<AppendWire>>(
+ pub fn append_with_outputs<A: Into<CircuitUnit>>(
  &mut self,
  op: impl Into<OpType>,
  inputs: impl IntoIterator<Item = A>,
@@ -107,9 +86,9 @@ impl<'a, T: Dataflow + ?Sized> CircuitBuilder<'a, T> {
  .into_iter()
  .map(Into::into)
  .enumerate()
- .map(|(input_port, a_w): (usize, AppendWire)| match a_w {
- AppendWire::W(wire) => Some(wire),
- AppendWire::I(wire_index) => {
+ .map(|(input_port, a_w): (usize, CircuitUnit)| match a_w {
+ CircuitUnit::Wire(wire) => Some(wire),
+ CircuitUnit::Linear(wire_index) => {
  linear_inputs.insert(input_port, wire_index);
  self.wires.get(wire_index).copied()
  }
@@ -187,7 +166,6 @@ mod test {
 
  #[test]
  fn with_nonlinear_and_outputs() {
- use AppendWire::{I, W};
  let build_res = build_main(
  Signature::new_df(type_row![QB, QB, F64], type_row![QB, QB, BIT]),
  |mut f_build| {
@@ -197,7 +175,10 @@ mod test {
 
  let measure_out = linear
  .append(LeafOp::CX, [0, 1])?
- .append_and_consume(LeafOp::RzF64, [I(0), W(angle)])?
+ .append_and_consume(
+ LeafOp::RzF64,
+ [CircuitUnit::Linear(0), CircuitUnit::Wire(angle)],
+ )?
  .append_with_outputs(LeafOp::Measure, [0])?;
 
  let out_qbs = linear.finish();

src/hugr.rs

@@ -90,11 +90,6 @@ pub struct Port {
 /// The direction of a port.
 pub type Direction = portgraph::Direction;
 
-#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
-/// A DataFlow wire, defined by a Value-kind output port of a node
-// Stores node and offset to output port
-pub struct Wire(Node, usize);
-
 /// Public API for HUGRs.
 impl Hugr {
  /// Applies a rewrite to the graph.
@@ -184,6 +179,11 @@ impl Port {
  }
 }
 
+#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
+/// A DataFlow wire, defined by a Value-kind output port of a node
+// Stores node and offset to output port
+pub struct Wire(Node, usize);
+
 impl Wire {
  /// Create a new wire from a node and a port.
  #[inline]
@@ -204,6 +204,31 @@ impl Wire {
  }
 }
 
+/// Enum for uniquely identifying the origin of linear wires in a circuit-like
+/// dataflow region.
+///
+/// Falls back to [`Wire`] if the wire is not linear or if it's not possible to
+/// track the origin.
+#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
+pub enum CircuitUnit {
+ /// Arbitrary input wire.
+ Wire(Wire),
+ /// Index to region input.
+ Linear(usize),
+}
+
+impl From<usize> for CircuitUnit {
+ fn from(value: usize) -> Self {
+ CircuitUnit::Linear(value)
+ }
+}
+
+impl From<Wire> for CircuitUnit {
+ fn from(value: Wire) -> Self {
+ CircuitUnit::Wire(value)
+ }
+}
+
 /// Errors that can occur while manipulating a Hugr.
 ///
 /// TODO: Better descriptions, not just re-exporting portgraph errors.