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AP_HAL_ChibiOS: allow setup for low noise clock mismatch tolerant UAR…
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bugobliterator committed Jul 17, 2024
1 parent c3e6236 commit cf52c86
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Showing 2 changed files with 12 additions and 4 deletions.
5 changes: 5 additions & 0 deletions libraries/AP_HAL_ChibiOS/UARTDriver.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -461,6 +461,11 @@ void UARTDriver::_begin(uint32_t b, uint16_t rxS, uint16_t txS)
sercfg.cr3 |= USART_CR3_DMAT;
}
sercfg.irq_cb = rx_irq_cb;
if (sdef.low_noise_line) {
// we can mark UART to sample on one bit instead of default 3 bits
// this allows us to be slightly less sensitive to clock differences
sercfg.cr3 |= USART_CR3_ONEBIT;
}
#endif // HAL_UART_NODMA
if (!(sercfg.cr2 & USART_CR2_STOP2_BITS)) {
sercfg.cr2 |= USART_CR2_STOP1_BITS;
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11 changes: 7 additions & 4 deletions libraries/AP_HAL_ChibiOS/hwdef/scripts/chibios_hwdef.py
Original file line number Diff line number Diff line change
Expand Up @@ -1899,12 +1899,12 @@ def write_UART_config(self, f):

if dev.startswith('OTG2'):
f.write(
'#define HAL_%s_CONFIG {(BaseSequentialStream*) &SDU2, 2, true, false, 0, 0, false, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, UINT8_MAX}\n' % dev) # noqa
'#define HAL_%s_CONFIG {(BaseSequentialStream*) &SDU2, 2, true, false, 0, 0, false, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, UINT8_MAX, false}\n' % dev) # noqa
OTG2_index = serial_list.index(dev)
self.dual_USB_enabled = True
elif dev.startswith('OTG'):
f.write(
'#define HAL_%s_CONFIG {(BaseSequentialStream*) &SDU1, 1, true, false, 0, 0, false, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, UINT8_MAX}\n' % dev) # noqa
'#define HAL_%s_CONFIG {(BaseSequentialStream*) &SDU1, 1, true, false, 0, 0, false, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, UINT8_MAX, false}\n' % dev) # noqa
else:
need_uart_driver = True
f.write(
Expand Down Expand Up @@ -1943,8 +1943,11 @@ def get_RTS_alt_function():
if s not in lib.AltFunction_map:
return "UINT8_MAX"
return lib.AltFunction_map[s]

f.write("%s}\n" % get_RTS_alt_function())
low_noise = 'false'
rx_port = dev + '_RX'
if rx_port in self.bylabel and self.bylabel[rx_port].has_extra('LOW_NOISE'):
low_noise = 'true'
f.write("%s, %s}\n" % (get_RTS_alt_function(), low_noise))

if have_rts_cts:
f.write('#define AP_FEATURE_RTSCTS 1\n')
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