Merge branch 'work/MiV-RV32IMAF-runtime' into 'master'

Add MiV-RV32IMAF runtime

See merge request eng/toolchain/bb-runtimes!105

arm/cortex-m1/microsemi/s-bbbopa.ads

@@ -40,6 +40,10 @@ package System.BB.Board_Parameters is
  -- Hardware clock --
  --------------------
 
- Clock_Frequency : constant := 50_000_000;
+ System_Clock : constant := 50_000_000;
+ -- Clock provided to the soft core
 
+ Clock_Frequency : constant := System_Clock;
+
+ UART_Base_Address : constant := 16#42000000#;
 end System.BB.Board_Parameters;

arm/cortexm.py

@@ -618,9 +618,9 @@ def __init__(self):
  self.add_gnat_sources(
  "arm/cortex-m1/microsemi/s-bbbopa.ads",
  "arm/cortex-m1/microsemi/s-bbmcpa.ads",
- "arm/cortex-m1/microsemi/s-textio.adb",
- "arm/cortex-m1/microsemi/svd/i-microsemi.ads",
- "arm/cortex-m1/microsemi/svd/i-microsemi-coreuartapb.ads",
+ "src/s-textio__coreuartapb.adb",
+ "src/i-microsemi-coreuartapb.ads",
+ "src/i-microsemi.ads",
  )
 
  self.add_gnarl_sources("arm/cortex-m1/microsemi/a-intnam.ads")

build_rts.py

@@ -59,9 +59,10 @@
 
 # riscv
 from riscv import (
- Spike,
- PolarFireSOC,
  HiFive1,
+ MIV_RV32IMAF,
+ PolarFireSOC,
+ Spike,
  RV32I,
  RV32IM,
  RV32IAC,
@@ -249,6 +250,8 @@ def build_configs(target):
  t = Spike()
  elif target == "hifive1":
  t = HiFive1()
+ elif target == "miv_rv32imaf":
+ t = MIV_RV32IMAF()
  elif target == "polarfiresoc":
  t = PolarFireSOC()
  elif target == "rv32i":

riscv/__init__.py

@@ -157,6 +157,19 @@ def target(self):
  def has_timer_64(self):
  return True
 
+ def dump_runtime_xml(self, rts_name, rts):
+ cnt = super(RiscV32, self).dump_runtime_xml(rts_name, rts)
+ if rts_name == "embedded":
+ cnt = cnt.replace(
+ '"-nostartfiles"', '"--specs=${RUNTIME_DIR(ada)}/link-zcx.spec"'
+ )
+ return cnt
+
+ def amend_rts(self, rts_profile, conf):
+ super(DFBBTarget, self).amend_rts(rts_profile, conf)
+ if rts_profile == "embedded":
+ conf.config_files.update({"link-zcx.spec": readfile("riscv/link-zcx.spec")})
+
 
 class HiFive1(RiscV32):
  @property
@@ -222,6 +235,78 @@ def __init__(self):
  )
 
 
+class MIV_RV32IMAF(RiscV32):
+ @property
+ def name(self):
+ return "miv_rv32imaf"
+
+ @property
+ def has_single_precision_fpu(self):
+ return True
+
+ @property
+ def has_double_precision_fpu(self):
+ return False
+
+ @property
+ def compiler_switches(self):
+ # The required compiler switches
+ return ("-march=rv32imaf_zicsr", "-mabi=ilp32f")
+
+ @property
+ def has_small_memory(self):
+ return True
+
+ @property
+ def loaders(self):
+ return ("RAM",)
+
+ @property
+ def system_ads(self):
+ return {
+ "light": "system-xi-riscv.ads",
+ "light-tasking": "system-xi-riscv-one-irq-prio-light-tasking.ads",
+ "embedded": "system-xi-riscv-one-irq-prio-full.ads",
+ }
+
+ @property
+ def readme_file(self):
+ return "riscv/microchip/miv_rv32imaf/README"
+
+ def __init__(self):
+ super(MIV_RV32IMAF, self).__init__()
+ self.add_linker_script("riscv/microchip/miv_rv32imaf/memory-map.ld")
+ self.add_linker_script(
+ "riscv/microchip/miv_rv32imaf/common-RAM.ld", loader="RAM"
+ )
+ self.add_gnat_sources(
+ "riscv/microchip/miv_rv32imaf/start-ram.S",
+ "riscv/sifive/fe310/svd/i-fe310.ads",
+ "riscv/sifive/fe310/svd/i-fe310-plic.ads",
+ "src/s-bbbopa__miv.ads",
+ "src/s-macres__none.adb",
+ "src/s-textio__coreuartapb.adb",
+ "src/i-microsemi-coreuartapb.ads",
+ "src/i-microsemi.ads",
+ "riscv/src/riscv_def.h",
+ )
+ self.add_gnarl_sources(
+ "riscv/microchip/miv_rv32imaf/a-intnam.ads",
+ "src/s-bbpara__riscv.ads",
+ "src/s-bbbosu__riscv.adb",
+ "src/s-bbsuti__riscv_clint.adb",
+ "src/s-bbsumu__generic.adb",
+ "src/s-bbcppr__new.ads",
+ "src/s-bbcppr__riscv.adb",
+ "src/s-bbcpsp__riscv.ads",
+ "src/s-bbcpsp__riscv.adb",
+ "riscv/src/context_switch.S",
+ "riscv/src/trap_handler.S",
+ "riscv/src/s-bbripl.ads",
+ "riscv/microchip/miv_rv32imaf/s-bbripl.adb",
+ )
+
+
 class RV32BASE(RiscV32):
  """
  Generic Light run-time meant to be used with the startup generator (crt0 and

riscv/microchip/miv_rv32imaf/README

@@ -0,0 +1,117 @@
+Microsemi MIV_RV32IMAF_L1_AHB Runtimes
+======================================
+
+This BSP supports the Microsemi MIV_RV32IMAF_L1_AHB softcore processor for
+the Microsemi FPGAs.
+
+Required FPGA IP
+----------------
+
+* MIV_RV32IMAF_L1_AHB
+* CoreUARTapb (for Ada.Text_IO)
+
+Runtimes Supported
+------------------
+
+* Light
+* Light Tasking
+* Embedded
+
+Using the runtimes
+------------------
+
+As a prerequisite, GNAT Pro for RISC-V32 ELF needs to be installed. To use the
+runtime, copy the runtime to the compiler installation or another location:
+
+(1) Compiler Installation
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Copy the runtime to the `<riscv32-elf gnat install>/riscv32-elf/lib/gnat/`
+folder. You can then select the runtime in GNAT Studio from the Toolchain pane
+of the Project Properties dialog box or set the following in your GPR file:
+
+ for Runtime ("ada") use "light-tasking-am64xr5";
+
+(2) Other Locations
+~~~~~~~~~~~~~~~~~~
+
+Move the runtime into another directory and then in the project file provide
+the full or relative path from the project file:
+
+ for Runtime ("ada") use "/path/to/runtime/embedded-miv_rv32imaf";
+
+Alternatively, you can set the GPR_RUNTIME_PATH to the folder containing the
+runtime to be able to just specify the runtime name.
+
+Rebuilding the Runtime
+----------------------
+
+If you need to make changes to the runtime's BSP you can rebuild with GPRbuild.
+
+For the Light runtime: gprbuild -P runtime_build.gpr
+
+For the Light-Tasking and Embedded runtimes: gprbuild -P ravenscar_build.gpr
+
+Note: if you were provided the runtime in a certification context, please reach
+out to AdaCore before modifying the runtime.
+
+Resources Used
+--------------
+
+The Light-Tasking and Embedded runtimes use the RISC-V mtime and mtimecmp
+registers to implement Ada semantics for time, i.e., delay statements and
+package Ada.Real_Time.
+
+Ada.Text_IO is configured to utilise the Microsemi CoreUARTapb IP. See the
+Text I/O section for more details.
+
+Memory Layout
+-------------
+
+The runtime is configured for the following memory space:
+
+ ram (rwx) : ORIGIN = 0x80000000, LENGTH = 512K
+ ram_io (rwx) : ORIGIN = 0x70000000, LENGTH = 512K
+
+The size of each region can be modified by updating the linker script in
+ld/memory-map.ld.
+
+A single loader option is provided: RAM. The RAM loader stores and runs the
+program out of RAM at the memory address 0x80000000. Both the memory-map.ld
+and common-RAM.ld may be modified to suit the application.
+
+System Clock
+------------
+
+The runtime is configured for a 80 MHz clock. If your MIV_RV32IMAF_L1_AHB is
+fed with a different clock rate, update the System_Clock constant in
+System.BB.Board_Parameters (gnat/s-bbbopa.ads) and rebuild the runtime.
+
+Interrupts
+----------
+
+The runtime supports 32 IRQ interrupts. Interrupt priorities are not supported
+by the Light Tasking and Embedded runtimes. The interrupt names are located in
+Ada.Interrupts.Names (gnarl/a-intnam.ads).
+
+Text I/O
+--------
+
+The runtime provides a minimal version of the Ada.Text_IO package supporting
+character- and string-based input and output routines for basic I/O needs. It
+is recommended to implement your own I/O packages based around your I/O
+channel of choice.
+
+The bodies of the Ada.Text_IO routines call through to a device-specific I/O
+package named System.Text_IO. See the package body in the file `s-textio.adb`
+in the gnat directory for more details.
+
+System.Text_IO is configured to use CoreUARTapb at address 16#6010_0000#, with
+a 115200 baud rate, one stop bit, no parity using system clock source. It
+implements a simple polling UART driver.
+
+The base address of the CoreUARTapb can be changed in System.BB.Parameters
+(gnat/s-bbbopa.ads). The CoreUARTapb configuration in System.Text_IO package
+may be modified as required.
+
+The user is free to use the CoreUARTapb device if Ada.Text_IO is not used.

riscv/microchip/miv_rv32imaf/a-intnam.ads

@@ -0,0 +1,61 @@
+--
+-- Copyright (C) 2023, AdaCore
+--
+
+-- This is a version for the MIV-RV32
+package Ada.Interrupts.Names is
+
+ -- All identifiers in this unit are implementation defined
+
+ pragma Implementation_Defined;
+
+ ----------------
+ -- Interrupts --
+ ----------------
+
+ -- System tick
+ Sys_Tick_Interrupt : constant Interrupt_ID := -1;
+
+ -- Target Specific Names
+
+ Timer_0 : constant Interrupt_ID := 8;
+ Timer_1 : constant Interrupt_ID := 12;
+ Console : constant Interrupt_ID := 15;
+ Timer_2 : constant Interrupt_ID := 20;
+ Timer_3 : constant Interrupt_ID := 26;
+
+ -- General IRQ Names
+
+ IRQ1 : constant Interrupt_ID := 1;
+ IRQ2 : constant Interrupt_ID := 2;
+ IRQ3 : constant Interrupt_ID := 3;
+ IRQ4 : constant Interrupt_ID := 4;
+ IRQ5 : constant Interrupt_ID := 5;
+ IRQ6 : constant Interrupt_ID := 6;
+ IRQ7 : constant Interrupt_ID := 7;
+ IRQ8 : constant Interrupt_ID := 8;
+ IRQ9 : constant Interrupt_ID := 9;
+ IRQ10 : constant Interrupt_ID := 10;
+ IRQ11 : constant Interrupt_ID := 11;
+ IRQ12 : constant Interrupt_ID := 12;
+ IRQ13 : constant Interrupt_ID := 13;
+ IRQ14 : constant Interrupt_ID := 14;
+ IRQ15 : constant Interrupt_ID := 15;
+ IRQ16 : constant Interrupt_ID := 16;
+ IRQ17 : constant Interrupt_ID := 17;
+ IRQ18 : constant Interrupt_ID := 18;
+ IRQ19 : constant Interrupt_ID := 19;
+ IRQ20 : constant Interrupt_ID := 20;
+ IRQ21 : constant Interrupt_ID := 21;
+ IRQ22 : constant Interrupt_ID := 22;
+ IRQ23 : constant Interrupt_ID := 23;
+ IRQ24 : constant Interrupt_ID := 24;
+ IRQ25 : constant Interrupt_ID := 25;
+ IRQ26 : constant Interrupt_ID := 26;
+ IRQ27 : constant Interrupt_ID := 27;
+ IRQ28 : constant Interrupt_ID := 28;
+ IRQ29 : constant Interrupt_ID := 29;
+ IRQ30 : constant Interrupt_ID := 30;
+ IRQ31 : constant Interrupt_ID := 31;
+
+end Ada.Interrupts.Names;