The RISC-V platform requirements for OpenSBI can change over time with advances in RISC-V specifications and ecosystem.
To handle this, we have two types of RISC-V platform requirements:
- Base platform requirements which apply to all OpenSBI releases
- Release specific platform requirements which apply to a OpenSBI release and later releases
Currently, we don't have any Release specific platform requirements but such platform requirements will be added in future.
The base RISC-V platform requirements for OpenSBI are as follows:
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At least rv32ima or rv64ima required on all HARTs
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At least one HART should have S-mode support because:
- SBI calls are meant for RISC-V S-mode (Supervisor mode)
- OpenSBI implements SBI calls for S-mode software
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The MTVEC CSR on all HARTs must support direct mode
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The PMP CSRs are optional. If PMP CSRs are not implemented then OpenSBI cannot protect M-mode firmware and secured memory regions
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The TIME CSR is optional. If TIME CSR is not implemented in hardware then a 64-bit MMIO counter is required to track time and emulate TIME CSR
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Hardware support for injecting M-mode software interrupts on a multi-HART platform
The RISC-V extensions not covered by rv32ima or rv64ima are optional for OpenSBI. Although, OpenSBI will detect and handle some of these optional RISC-V extensions at runtime.
The optional RISC-V extensions handled by OpenSBI at runtime are:
- D-extension: Double precision floating point
- F-extension: Single precision floating point
- H-extension: Hypervisor