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Positional instantiation. #61

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futurehome opened this issue Apr 12, 2023 · 1 comment

futurehome commented Apr 12, 2023

Hi,

For positional instantiation, seems the first port will always be output and others will be input?

Collaborator

drom commented Jul 16, 2023 •

edited

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In Verilog, any argument can be any directionality

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