From 7910d3ecf20385da054a83786841b3706ddb82ee Mon Sep 17 00:00:00 2001 From: matth2k Date: Sat, 9 Dec 2023 22:49:13 -0500 Subject: [PATCH 01/29] new blog post for project --- content/2023-12-09-allo-amc/index.md | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 content/2023-12-09-allo-amc/index.md diff --git a/content/2023-12-09-allo-amc/index.md b/content/2023-12-09-allo-amc/index.md new file mode 100644 index 000000000..0c793cb15 --- /dev/null +++ b/content/2023-12-09-allo-amc/index.md @@ -0,0 +1,16 @@ ++++ +title = "Frontend Integration for AMC (Accelerator Memory Compiler)" +[extra] +bio = """ + Matthew Hofmann is a 2nd year Ph.D. student researching design automation for reconfigurable hardware. + Yixiao Du is a 3rd year Ph.D. student researching hardware acceleration for graph processing and sparse linear algebra. +""" +[[extra.authors]] +name = "Matthew Hofmann" +[[extra.authors]] +name = "Yixiao Du" ++++ + +## Summary + +TODO \ No newline at end of file From e6e2a86ae5b50fef9097026e577372997489abda Mon Sep 17 00:00:00 2001 From: matth2k Date: Sun, 10 Dec 2023 05:50:56 -0500 Subject: [PATCH 02/29] add Design Example section --- content/2023-12-09-allo-amc/index.md | 160 ++++++++++++++++++++++++++- 1 file changed, 157 insertions(+), 3 deletions(-) diff --git a/content/2023-12-09-allo-amc/index.md b/content/2023-12-09-allo-amc/index.md index 0c793cb15..ffc7d251c 100644 --- a/content/2023-12-09-allo-amc/index.md +++ b/content/2023-12-09-allo-amc/index.md @@ -2,7 +2,7 @@ title = "Frontend Integration for AMC (Accelerator Memory Compiler)" [extra] bio = """ - Matthew Hofmann is a 2nd year Ph.D. student researching design automation for reconfigurable hardware. + Matthew Hofmann is a 2nd year Ph.D. student researching design automation for reconfigurable hardware.
Yixiao Du is a 3rd year Ph.D. student researching hardware acceleration for graph processing and sparse linear algebra. """ [[extra.authors]] @@ -11,6 +11,160 @@ name = "Matthew Hofmann" name = "Yixiao Du" +++ -## Summary +## Introduction -TODO \ No newline at end of file +### Custom Hardware Accelerators + +TODO + +### High Level Synthesis + +TODO + +### MLIR and Incubator Projects + +TODO(introduce MLIR, CIRCT, hcl, amc dialects) + +## Design Example + +To use Allo with AMC, the designer writes their kernel in Python. Then, then user can simply specify which Python function to build with the AMC backend. Moreover, AMC acts a drop-in replacement to the other backends in the Allo ecosystem, making functional testing and debugging seamless. In the far majority of cases, the [NumPy](https://numpy.org/) or the LLVM backend is suitable for use as a golden reference model. In this section, we walk through an example where we functionally verify a kernel built with AMC. Then, we will record some resource estimates and execution times. + +Our illustrative example will be verifying matrix multiplication. What would ordinarily be a cumbersome task when using the vendor tools, like [Vitis HLS](https://www.xilinx.com/products/design-tools/vitis/vitis-hls.html), becomes a simple, 5 minute exercise. First, we specify some inputs initialized to random values. Then, `build()` the accelerator. Finally, we call both the software and hardware simulations and check their outputs. Compared to a C/C++ based tool flow, the amount of boilerplate code and scripting is reduced to near zero. In the end, we can represent this application with only 18 lines of code: + +```python +def test_amc(): + N = 16 + # Initialize 2 input matricies to random integers + A = np.random.randint(0, 20, size=(N, N), dtype="int32") + B = np.random.randint(0, 20, size=(N, N), dtype="int32") + + # Our kernel is just matrix multiplication + def kernel(A: int32[N, N], B: int32[N, N]) -> int32[N, N]: + return matmul(A, B) + + # Build the accelerator with AMC backend + s = allo.customize(kernel) + f = s.build(target="amc") + # Run the software simulation by invoking directly + np_out = kernel(A, B) + # Now run the hardware simulation with AMC + allo_out = f(A, B) + np.testing.assert_array_equal(allo_out, np_out) +``` + +Additionally, we can also get an approximation of how much FPGA resources this design uses. Simply call `.get_resource_estimates()` after building: + +```python + print(f.get_resource_estimates()) + # { + # "BRAM36": 1, + # "DSP": 3, + # "FF": 255, + # "LUT": 467, + # "LUTL": 467, + # "LUTM": 0, + # "cycles": 15016, + # "name": "kernel" + # } +``` + +This uses [Vivado](https://www.xilinx.com/products/design-tools/vivado.html) RTL synthesis for Xilinx FPGAs, but it would only be a one-time effort to support other synthesis tools like [Yosys](https://yosyshq.net/yosys/). If errors arise, the AMC backend offers some options to help with debugging. To better understand what is going on under the hood, the first step would be to dump the underlying intermediate representation in MLIR with `print(f.module)`. + +```mlir +// print(f.module) +func.func @kernel(%arg0: memref<16x16xi32>, %arg1: memref<16x16xi32>) -> memref<16x16xi32> attributes {itypes = "ss", otypes = "s", top} { + %c0_i32 = arith.constant 0 : i32 + %alloc = memref.alloc() : memref<16x16xi32> + affine.for %arg2 = 0 to 16 { + affine.for %arg3 = 0 to 16 { + affine.store %c0_i32, %alloc[%arg2, %arg3] : memref<16x16xi32> + } + } + affine.for %arg2 = 0 to 16 { + affine.for %arg3 = 0 to 16 { + affine.for %arg4 = 0 to 16 { + %0 = affine.load %arg0[%arg2, %arg4] : memref<16x16xi32> + %1 = affine.load %arg1[%arg4, %arg3] : memref<16x16xi32> + %2 = affine.load %alloc[%arg2, %arg3] : memref<16x16xi32> + %3 = arith.muli %0, %1 : i32 + %4 = arith.addi %2, %3 : i32 + affine.store %4, %alloc[%arg2, %arg3] : memref<16x16xi32> + } + } + } + return %alloc : memref<16x16xi32> +} +``` + +To debug , we can inspect individual steps of the lowering pipline. For example, here is what this application would look like after AMC buffers are inserted: + +```mlir +module { + amc.memory @amcMemory0(!amc.static_port<16x16xi32, w, 1>, !amc.static_port<16x16xi32, rw, 1>) { + %0 = amc.alloc : !amc.memref<16x16xi32> + %1 = amc.create_port(%0 : !amc.memref<16x16xi32>) : !amc.static_port<16x16xi32, w, 1> + %2 = amc.create_port(%0 : !amc.memref<16x16xi32>) : !amc.static_port<16x16xi32, rw, 1> + amc.extern %1, %2 : !amc.static_port<16x16xi32, w, 1>, !amc.static_port<16x16xi32, rw, 1> + } + func.func @kernel(%arg0: memref<16x16xi32>, %arg1: memref<16x16xi32>, %arg2: memref<16x16xi32>) attributes {itypes = "ss", otypes = "s", top} { + %c0_i32 = arith.constant 0 : i32 + %0:2 = amc.inst @amcMemory0_inst of @amcMemory0 : !amc.static_port<16x16xi32, w, 1>, !amc.static_port<16x16xi32, rw, 1> + affine.for %arg3 = 0 to 16 { + affine.for %arg4 = 0 to 16 { + amc.affine_store %c0_i32, %0#0[%arg3, %arg4] : !amc.static_port<16x16xi32, w, 1> + } {hls.pipeline, hls.unroll = 1 : i64} + } {hls.unroll = 1 : i64} + affine.for %arg3 = 0 to 16 { + affine.for %arg4 = 0 to 16 { + affine.for %arg5 = 0 to 16 { + %1 = affine.load %arg0[%arg3, %arg5] : memref<16x16xi32> + %2 = affine.load %arg1[%arg5, %arg4] : memref<16x16xi32> + %3 = amc.affine_load %0#1[%arg3, %arg4] : !amc.static_port<16x16xi32, rw, 1> + %4 = arith.muli %1, %2 : i32 + %5 = arith.addi %3, %4 : i32 + amc.affine_store %5, %0#1[%arg3, %arg4] : !amc.static_port<16x16xi32, rw, 1> + } {hls.pipeline, hls.unroll = 1 : i64} + } {hls.unroll = 1 : i64} + } {hls.unroll = 1 : i64} + affine.for %arg3 = 0 to 16 { + affine.for %arg4 = 0 to 16 { + %1 = amc.affine_load %0#1[%arg3, %arg4] : !amc.static_port<16x16xi32, rw, 1> + affine.store %1, %arg2[%arg3, %arg4] : memref<16x16xi32> + } {hls.bufferize, hls.pipeline, hls.unroll = 1 : i64} + } {hls.unroll = 1 : i64} + return + } +} +``` + +For more information on the motivation behin AMC and the dialect itself, you can visit the [Andrew Butt's blog post](https://www.cs.cornell.edu/courses/cs6120/2022sp/blog/banked-memory-compiler-backend-in-mlir/) from last year. As a last resort when debugging, the AMC backend has a `.dump_vcd()` method: + +```python + f.dump_vcd("waveform.vcd") + # You can now take the debugging to your favorite waveform viewer +``` + +## Tool flow + +To use Allo with AMC, The Allo frontend automates all the stages of the tool flow. Nonetheless, understanding each component + +### Overview + +### Allo + +### AMC + +TODO. Show pass pipeline + +## Results + +TODO + +## Future Work + +TODO +- Fix how allow constructs affine for. Needs to Store to load forward + +## Conclusion + +The project was by and large a success, because we have achieved a much higher level of automation in evaluating the AMC+Calyx toolflow. Being able to write HLS kernels with `numpy` and run the RTL simulation as a normal function call greatly reduces the amount of effort in adding a new test case. Moreover, the `.dump_vcd()` and `.get_resource_estimates()` provide more tools for debugging without having to manually interact with the synthesis tools. \ No newline at end of file From 81f933c196002efda0af9701418934a72707ff6b Mon Sep 17 00:00:00 2001 From: matth2k Date: Sun, 10 Dec 2023 06:49:48 -0500 Subject: [PATCH 03/29] start intro --- content/2023-12-09-allo-amc/index.md | 32 ++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/content/2023-12-09-allo-amc/index.md b/content/2023-12-09-allo-amc/index.md index ffc7d251c..a0f573d99 100644 --- a/content/2023-12-09-allo-amc/index.md +++ b/content/2023-12-09-allo-amc/index.md @@ -13,6 +13,8 @@ name = "Yixiao Du" ## Introduction +For our final course project, we have integrated our HLS (high-level sythesis) compiler, AMC, with a Python frontend, called Allo. In the end, we are able to compile and simulate custom hardware designs with extremely concise design descriptions and short compile times. As a consequence, we greatly reduce the design effort required for new accelerators as well as offer a convenient tool for functional verification. In this report, we walk through an example design with our tool flow, offer insight into how the underlying compiler works, and finally evaluate some benchmarks with latency and resource utilization measurements. + ### Custom Hardware Accelerators TODO @@ -27,9 +29,9 @@ TODO(introduce MLIR, CIRCT, hcl, amc dialects) ## Design Example -To use Allo with AMC, the designer writes their kernel in Python. Then, then user can simply specify which Python function to build with the AMC backend. Moreover, AMC acts a drop-in replacement to the other backends in the Allo ecosystem, making functional testing and debugging seamless. In the far majority of cases, the [NumPy](https://numpy.org/) or the LLVM backend is suitable for use as a golden reference model. In this section, we walk through an example where we functionally verify a kernel built with AMC. Then, we will record some resource estimates and execution times. +To use Allo with AMC, the designer only needs to write their kernel in Python. Then, then user can simply specify which Python function to build with the AMC backend. Moreover, AMC acts a drop-in replacement to the other backends in the Allo ecosystem, making functional testing and debugging seamless. In the far majority of cases, the [NumPy](https://numpy.org/) or the LLVM backend is suitable for use as a golden reference model. In this section, we walk through an example where we functionally verify a kernel built with AMC. Then, we will record some resource estimates and execution times. -Our illustrative example will be verifying matrix multiplication. What would ordinarily be a cumbersome task when using the vendor tools, like [Vitis HLS](https://www.xilinx.com/products/design-tools/vitis/vitis-hls.html), becomes a simple, 5 minute exercise. First, we specify some inputs initialized to random values. Then, `build()` the accelerator. Finally, we call both the software and hardware simulations and check their outputs. Compared to a C/C++ based tool flow, the amount of boilerplate code and scripting is reduced to near zero. In the end, we can represent this application with only 18 lines of code: +Our illustrative example will be matrix multiplication. What would ordinarily be a cumbersome task when using the vendor tools, like [Vitis HLS](https://www.xilinx.com/products/design-tools/vitis/vitis-hls.html), becomes a simple, 5 minute exercise. First, we specify some inputs initialized to random values. Then, `build()` the accelerator. Finally, we call both the software and hardware simulations and check their outputs. Compared to a C/C++ based tool flow, the amount of boilerplate code and scripting is reduced to near zero. In the end, we can represent this application with only 18 lines of code: ```python def test_amc(): @@ -68,7 +70,7 @@ Additionally, we can also get an approximation of how much FPGA resources this d # } ``` -This uses [Vivado](https://www.xilinx.com/products/design-tools/vivado.html) RTL synthesis for Xilinx FPGAs, but it would only be a one-time effort to support other synthesis tools like [Yosys](https://yosyshq.net/yosys/). If errors arise, the AMC backend offers some options to help with debugging. To better understand what is going on under the hood, the first step would be to dump the underlying intermediate representation in MLIR with `print(f.module)`. +This uses [Vivado](https://www.xilinx.com/products/design-tools/vivado.html) RTL synthesis for Xilinx FPGAs, but it would only be a one-time effort to support other synthesis tools like [Yosys](https://yosyshq.net/yosys/). If functional errors arise, the AMC backend also offers some options to help with debugging. To better understand what is going on under the hood, the first step would be to dump the underlying intermediate representation in MLIR with `print(f.module)`. ```mlir // print(f.module) @@ -96,7 +98,7 @@ func.func @kernel(%arg0: memref<16x16xi32>, %arg1: memref<16x16xi32>) -> memref< } ``` -To debug , we can inspect individual steps of the lowering pipline. For example, here is what this application would look like after AMC buffers are inserted: +The above IR helps give insight into what program the AMC is actually attempting to compile. To debug at a lower level, we can inspect the IR at individual steps of the pass pipeline. For example, here is what this application would look like after AMC buffers are inserted: ```mlir module { @@ -137,16 +139,34 @@ module { } ``` -For more information on the motivation behin AMC and the dialect itself, you can visit the [Andrew Butt's blog post](https://www.cs.cornell.edu/courses/cs6120/2022sp/blog/banked-memory-compiler-backend-in-mlir/) from last year. As a last resort when debugging, the AMC backend has a `.dump_vcd()` method: +For more information on the motivation behind AMC and the dialect itself, you can visit the [Andrew Butt's blog post](https://www.cs.cornell.edu/courses/cs6120/2022sp/blog/banked-memory-compiler-backend-in-mlir/) from last year. As a last resort when debugging, the AMC backend has a `.dump_vcd()` method which outputs the waveforms from the hardware simulation: ```python f.dump_vcd("waveform.vcd") # You can now take the debugging to your favorite waveform viewer ``` +Writing other types of kernels is as easy as writing normal Python. For example, here are a handful of other kernels which are just a simple to get up and running: + +```python +def fibonnaci(A: uint32[N]): + A[1] = 1 + for i in range(2, N): + A[i] = A[i - 1] + A[i - 2] + +def vadd(A: uint32[N], B: uint32[N]) -> uint32[N]: + return A + B +``` + +Outside of what is shown here, the Allo DSL allows much more elaborate kernels and control over compute customizations, like loop tiling and reuse buffers. One again, you can get more information on Allo and its MLIR dialect by reading last years blog post by [Hongzheng Chen](https://www.cs.cornell.edu/courses/cs6120/2022sp/blog/hcl-mlir/). + +To conclude, we hope this example demonstrates the usefulness of the Allo frontend for high-level hardware design and further development of the AMC HLS compiler. As far as we are aware, the only other frameworks using Python to drive FPGA high-level synthesis are [LeFlow](https://arxiv.org/abs/1807.05317) and [PyLog](https://ieeexplore.ieee.org/document/9591456). However, neither of these efforts are using a homebrewed HLS compiler like us. + ## Tool flow -To use Allo with AMC, The Allo frontend automates all the stages of the tool flow. Nonetheless, understanding each component +Under the hood, the Allo frontend is automating all the interactions with other tools, IRs, and frameworks. Nonetheless, understanding each component is important to understanding the novelty in our approach. + +TODO(explain all the steps) ### Overview From e50c11f0288efb5e8748ad3c2395cfecc9266865 Mon Sep 17 00:00:00 2001 From: matth2k Date: Sun, 10 Dec 2023 07:04:39 -0500 Subject: [PATCH 04/29] add a few results --- content/2023-12-09-allo-amc/index.md | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/content/2023-12-09-allo-amc/index.md b/content/2023-12-09-allo-amc/index.md index a0f573d99..cc64d6091 100644 --- a/content/2023-12-09-allo-amc/index.md +++ b/content/2023-12-09-allo-amc/index.md @@ -178,7 +178,12 @@ TODO. Show pass pipeline ## Results -TODO +| Benchmark | Latency (Cycles) | LUTs | FFs | BRAM36s | DSPs | +| ------------- | ---------------- | ---- | --- | ------- | ---- | +| matmul16x16 | 15016 | 467 | 255 | 1 | 3 | +| spmv20x20 | 48 | 183 | 309 | 0 | 3 | +| vadd20 | 112 | 612 | 305 | 2 | 0 | +| fibonacci20 | 77 | 120 | 151 | 0 | 0 | ## Future Work From 3917edefec1b8fdc90ed7f355ea917fced850cb0 Mon Sep 17 00:00:00 2001 From: matth2k Date: Sun, 10 Dec 2023 07:10:12 -0500 Subject: [PATCH 05/29] add image of amc passes --- content/2023-12-09-allo-amc/amc_passes.png | Bin 0 -> 177900 bytes 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 content/2023-12-09-allo-amc/amc_passes.png diff --git a/content/2023-12-09-allo-amc/amc_passes.png b/content/2023-12-09-allo-amc/amc_passes.png new file mode 100644 index 0000000000000000000000000000000000000000..90dbfecccd087498676b71a9fef48c198a85753c GIT binary patch literal 177900 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z?9KPH&>qtE=K~6kFGbKp&`lmMFP|=JDFv;A^`CLT`^u`U)@Ch|c(+zJM?z62%2hiD z=lHGdc3-GtQKvPn@AUMj+)+S_B8(YBB-3lJ8CklAU%uN^p-SjK2hTlmo~bnuN#V=6 zm^{vD%?f|nGb2g0@lJ0iOc=6YFBs!IUEXKU>UPu}K7PsI^P9ypPLxBrZpu-BiXx06G8=v0a;XW+5K@>9(R>Az%1$kQr<}*Zw(2Mv-LoI;mP=#4rwfD0!j%8p@D=QdQ&(u2?A5Y1q6+DkB5dGLq~%*-qt5o z)0bk~hepd;xuA}`v?3<53orD3+Exo_uckQ$)|kd0Bceb~9y1RYn_=cty1#Jr5(Mg2 zh_Vs|rdAuJtR;HMs_9!`7erljLNDy=xaFx{{zng5H0L~eUiTq(EYoK z;cvOy`SJf2{f{XA4-gXyBI3b*n|g!0Z_$TD1fTK4$A6BC|Nrg#O%BJ0gUWt4^V_$Q NlTwx}eQWgTe*vl?*q8tS literal 0 HcmV?d00001 From 120a59ba6dd81a1366c6106825185b4fda1e54ef Mon Sep 17 00:00:00 2001 From: matth2k Date: Sun, 10 Dec 2023 07:13:17 -0500 Subject: [PATCH 06/29] reformat mlir --- content/2023-12-09-allo-amc/index.md | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/content/2023-12-09-allo-amc/index.md b/content/2023-12-09-allo-amc/index.md index cc64d6091..bef10e9cd 100644 --- a/content/2023-12-09-allo-amc/index.md +++ b/content/2023-12-09-allo-amc/index.md @@ -108,9 +108,10 @@ module { %2 = amc.create_port(%0 : !amc.memref<16x16xi32>) : !amc.static_port<16x16xi32, rw, 1> amc.extern %1, %2 : !amc.static_port<16x16xi32, w, 1>, !amc.static_port<16x16xi32, rw, 1> } - func.func @kernel(%arg0: memref<16x16xi32>, %arg1: memref<16x16xi32>, %arg2: memref<16x16xi32>) attributes {itypes = "ss", otypes = "s", top} { + func.func @kernel(%arg0: memref<16x16xi32>, %arg1: memref<16x16xi32>, %arg2: memref<16x16xi32>) { %c0_i32 = arith.constant 0 : i32 - %0:2 = amc.inst @amcMemory0_inst of @amcMemory0 : !amc.static_port<16x16xi32, w, 1>, !amc.static_port<16x16xi32, rw, 1> + %0:2 = amc.inst @amcMemory0_inst of @amcMemory0 + : !amc.static_port<16x16xi32, w, 1>, !amc.static_port<16x16xi32, rw, 1> affine.for %arg3 = 0 to 16 { affine.for %arg4 = 0 to 16 { amc.affine_store %c0_i32, %0#0[%arg3, %arg4] : !amc.static_port<16x16xi32, w, 1> From f49578412b12267190705b6efc54a12341bdb65a Mon Sep 17 00:00:00 2001 From: matth2k Date: Sun, 10 Dec 2023 10:07:03 -0500 Subject: [PATCH 07/29] fill in AMC section --- content/2023-12-09-allo-amc/index.md | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/content/2023-12-09-allo-amc/index.md b/content/2023-12-09-allo-amc/index.md index bef10e9cd..6e7d32a87 100644 --- a/content/2023-12-09-allo-amc/index.md +++ b/content/2023-12-09-allo-amc/index.md @@ -175,7 +175,19 @@ TODO(explain all the steps) ### AMC -TODO. Show pass pipeline +AMC (Accelerator Memory Compiler) is an entirely new plane of intermediate representation dedicated to representing memory architecture. To explain the need for such a dialect, the current state of conventional high-level synthesis compilers must be understood. As a brief summary, current HLS tools lacks an expressive model of memory, and it takes great manual effort to unlock the power of spatial architectures. This is by and large a consequence of the chosen source language. Most HLS compilers have a C/C++ frontend and LLVM middle end. As a consequence, every HLS compiler also has a set of compiler directives (`#pragma`'s) to fill in the semantic gaps of compiling to spatial hardware. For example, there are pragmas for partitioning memories, instantiating FIFOs, loop pipelining, and much more. By not having first class constructs for these design elements, optimization becomes tightly-coupled with source rewrites and HLS falls flat on its promises of high productivity. For the interested reader, we think this [blog post](https://specbranch.com/posts/fpgas-what-happened/) helps explain the current state of the FPGA accelerators for outsiders. + +Back to AMC, the custom dialect elaborates the *real* limiting resources of memory on spatial architectures: the ports. Each embedded block RAM on the FPGA has only two ports, and it takes an intelligent design methodology to utilize these memories in such a way that maximizes performance. AMC eliminates the guessing game by elaborating the description of the memory subsystem and optimizing it for the program at hand. To accompany the AMC dialect, we use [Calyx IR](https://calyxir.org/) to represent the control logic of the scheduled program. + + + +The following diagram shows the full pass pipeline of compiling the core MLIR dialects to Verilog: + +

+Diagram for AMC pass pipeline +
## Results From 1d106fe133ecf3b8813b5cdf0b08dc1b63bfe45f Mon Sep 17 00:00:00 2001 From: matth2k Date: Sun, 10 Dec 2023 10:11:03 -0500 Subject: [PATCH 08/29] code fmt --- content/2023-12-09-allo-amc/index.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/content/2023-12-09-allo-amc/index.md b/content/2023-12-09-allo-amc/index.md index 6e7d32a87..ad3bf3839 100644 --- a/content/2023-12-09-allo-amc/index.md +++ b/content/2023-12-09-allo-amc/index.md @@ -74,7 +74,7 @@ This uses [Vivado](https://www.xilinx.com/products/design-tools/vivado.html) RTL ```mlir // print(f.module) -func.func @kernel(%arg0: memref<16x16xi32>, %arg1: memref<16x16xi32>) -> memref<16x16xi32> attributes {itypes = "ss", otypes = "s", top} { +func.func @kernel(%arg0: memref<16x16xi32>, %arg1: memref<16x16xi32>) -> memref<16x16xi32> { %c0_i32 = arith.constant 0 : i32 %alloc = memref.alloc() : memref<16x16xi32> affine.for %arg2 = 0 to 16 { From 7bcfe13ab686a615e011943a8525d7bbe1fbe1a6 Mon Sep 17 00:00:00 2001 From: matth2k Date: Sun, 10 Dec 2023 10:13:53 -0500 Subject: [PATCH 09/29] assume C is initialized for brevity --- content/2023-12-09-allo-amc/index.md | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/content/2023-12-09-allo-amc/index.md b/content/2023-12-09-allo-amc/index.md index ad3bf3839..2a392c3dd 100644 --- a/content/2023-12-09-allo-amc/index.md +++ b/content/2023-12-09-allo-amc/index.md @@ -77,11 +77,6 @@ This uses [Vivado](https://www.xilinx.com/products/design-tools/vivado.html) RTL func.func @kernel(%arg0: memref<16x16xi32>, %arg1: memref<16x16xi32>) -> memref<16x16xi32> { %c0_i32 = arith.constant 0 : i32 %alloc = memref.alloc() : memref<16x16xi32> - affine.for %arg2 = 0 to 16 { - affine.for %arg3 = 0 to 16 { - affine.store %c0_i32, %alloc[%arg2, %arg3] : memref<16x16xi32> - } - } affine.for %arg2 = 0 to 16 { affine.for %arg3 = 0 to 16 { affine.for %arg4 = 0 to 16 { @@ -112,11 +107,6 @@ module { %c0_i32 = arith.constant 0 : i32 %0:2 = amc.inst @amcMemory0_inst of @amcMemory0 : !amc.static_port<16x16xi32, w, 1>, !amc.static_port<16x16xi32, rw, 1> - affine.for %arg3 = 0 to 16 { - affine.for %arg4 = 0 to 16 { - amc.affine_store %c0_i32, %0#0[%arg3, %arg4] : !amc.static_port<16x16xi32, w, 1> - } {hls.pipeline, hls.unroll = 1 : i64} - } {hls.unroll = 1 : i64} affine.for %arg3 = 0 to 16 { affine.for %arg4 = 0 to 16 { affine.for %arg5 = 0 to 16 { From 05d1d5e1b6d37fa7700661dd3c5521112a9b418a Mon Sep 17 00:00:00 2001 From: matth2k Date: Sun, 10 Dec 2023 11:42:04 -0500 Subject: [PATCH 10/29] add results section --- content/2023-12-09-allo-amc/index.md | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/content/2023-12-09-allo-amc/index.md b/content/2023-12-09-allo-amc/index.md index 2a392c3dd..a5910b9fa 100644 --- a/content/2023-12-09-allo-amc/index.md +++ b/content/2023-12-09-allo-amc/index.md @@ -141,6 +141,7 @@ Writing other types of kernels is as easy as writing normal Python. For example, ```python def fibonnaci(A: uint32[N]): + A[0] = 1 A[1] = 1 for i in range(2, N): A[i] = A[i - 1] + A[i - 2] @@ -181,6 +182,9 @@ The following diagram shows the full pass pipeline of compiling the core MLIR di ## Results +In this section, we report the latency and resource measures of a select set of micro-benchmarks. By using small testcases, we have the best chance of understanding how the high-level constructs are being mapped to hardware and where the compiler inefficiencies lie. With that said, here are a table of benchmarks compiled with our toolflow versus Vitis C HLS. + +**AMC** | Benchmark | Latency (Cycles) | LUTs | FFs | BRAM36s | DSPs | | ------------- | ---------------- | ---- | --- | ------- | ---- | | matmul16x16 | 15016 | 467 | 255 | 1 | 3 | @@ -188,6 +192,24 @@ The following diagram shows the full pass pipeline of compiling the core MLIR di | vadd20 | 112 | 612 | 305 | 2 | 0 | | fibonacci20 | 77 | 120 | 151 | 0 | 0 | +**Vitis 2022** +| Benchmark | Latency (Cycles) | LUTs | FFs | BRAM36s | DSPs | +| ------------- | ---------------- | ---- | --- | ------- | ---- | +| matmul16x16 | 5409 | 221 | 74 | 0 | 3 | +| spmv20x20 | 42 | 249 | 145 | 0 | 3 | +| vadd20 | 22 | 81 | 13 | 0 | 3 | +| fibonacci20 | 41 | 226 | 50 | 0 | 0 | + +**Difference: AMC - Vitis** +| Benchmark | Latency (Cycles) | LUTs | FFs | BRAM36s | DSPs | +| ------------- | ---------------- | ----- | ------ | ------- | ----- | +| matmul16x16 | +170% | +110% | +240% | - | +0% | +| spmv20x20 | +14% | -26% | +110% | - | +0% | +| vadd20 | +410% | +760% | +2200% | - | -300% | +| fibonacci20 | +88% | -47% | +200% | - | - | + +The main story here is revealed when looking at the core MLIR dialects Allo is emitting after parsing the AST. Inefficiencies in how Allo infers data types and creates `affine.for` loop nests is creating way too many redundant memory operations. For example, Allo is not using store-to-load forwarding between loop iterations. Even worse, Allo tries to explicity infer data type conversions when using operations that change the data width (e.g. 32b + 32b = 33b). This for some reason is causing extra memory copy loops to convert an entire memory before it is used. We anticipate that fixing the Allo frontend to produce higher-quality loops will take some time, as it depends on some level of memory dependence analysis. Nonetheless, it will be a very important improvement to make in order to reach similar latencies as what Vitis can produce with C code. + ## Future Work TODO From 22ecd538f8e18869197da4a984faf7fbaf800e48 Mon Sep 17 00:00:00 2001 From: Yixiao Du Date: Sun, 10 Dec 2023 15:44:49 -0500 Subject: [PATCH 11/29] finish intro; add Allo example: --- content/2023-12-09-allo-amc/index.md | 50 ++++++++++++++++++++++------ 1 file changed, 40 insertions(+), 10 deletions(-) diff --git a/content/2023-12-09-allo-amc/index.md b/content/2023-12-09-allo-amc/index.md index a5910b9fa..5fa5fd651 100644 --- a/content/2023-12-09-allo-amc/index.md +++ b/content/2023-12-09-allo-amc/index.md @@ -15,21 +15,23 @@ name = "Yixiao Du" For our final course project, we have integrated our HLS (high-level sythesis) compiler, AMC, with a Python frontend, called Allo. In the end, we are able to compile and simulate custom hardware designs with extremely concise design descriptions and short compile times. As a consequence, we greatly reduce the design effort required for new accelerators as well as offer a convenient tool for functional verification. In this report, we walk through an example design with our tool flow, offer insight into how the underlying compiler works, and finally evaluate some benchmarks with latency and resource utilization measurements. -### Custom Hardware Accelerators +### Hardware Accelerators -TODO +Hardware accelerators have been a promising way of improving the performance and energy efficiency of compute intensive applications. However, the design effort required to create a new accelerator is often too high for the average programmer. This is because the design process requires a deep understanding of the underlying hardware architecture and the tools used to compile the design. For example, the designer must understand how to map their algorithm to the hardware, how to optimize for the target (e.g., FPGAs), and how to debug the design. Moreover, the designer must also understand the tool flow, which includes the hardware description language (HDL), the synthesis tools, and the simulation tools. In the end, the designer must be an expert in both hardware and software to create a new accelerator. As a result, bringing up a new accelerator is a slow and sometimes tedious process. -### High Level Synthesis +### High-Level Synthesis -TODO +High-Level Synthesis (HLS) is a rising solution to the problem of hardware design productivity. The idea is to raise the level of abstraction of HDLs from the commonly-used register transfer level (RTL) to a higher-level language like C/C++. This allows the designer to focus more on the algorithm and less on the hardware details such as interfacing and timing. The core part of HLS it a compiler which infers a mapping from the high-level language to the hardware, which is often done by scheduling, resource allocation, and binding. In the end, the HLS compiler outputs RTL code to be synthesized by downstream tools. However, current HLS tools are not able to fully free designers from understanding hardware architectures. They often rely on special directives (e.g., C++ pragmas) from the designer to guide the optimization process. Sometimes, the designer must even rewrite their code to fit the HLS compiler's model of computation. ### MLIR and Incubator Projects -TODO(introduce MLIR, CIRCT, hcl, amc dialects) +Improving HLS with advanced compiler techniques is a very active area of research. There are many outstanding HLS tools/frameworks such as [TAPA](https://tapa.readthedocs.io/en/release/overview/overview.html), [Dynamatic](https://dynamatic.epfl.ch/), and [HeteroCL](https://heterocl.csl.cornell.edu/). However, these tools are developed independently with different compilation flows, which brings difficulties of integrating them together. [MLIR](https://mlir.llvm.org/) is a new compiler design paradigm where the source language is compiled through multiple levels of modularized intermediate representations (IRs), also known as dialects. Dialects act like domain-specific languages (DSLs) and can capture the approprate details at each level of abstraction. + +The [CIRCT](https://circt.llvm.org/) project proposes an MLIR-based development methodology for hardware design. It represents key components of hardware as MLIR dialects such as finite state machines (FSM), pipelines, and interface handshaking. HeteroCL has been migrated to the MLIR ecosystem as a dialect, with a new Python frontend called Allo. Allo decouples algorithm, optimization, and backend targets to enable productive hardware design and testing. Accelerator Memory Compiler (AMC) is an MLIR dialect for representing memory architecture. It captures common memory constructs such as partitioning, banking, and arbitration. AMC can be further lowered to Calyx, which is a part of the CIRCT system, and finally to synthesizable Verilog. In this project, we integrate Allo and AMC to enable a Python frontend for AMC. This allows us to use Allo to describe the algorithm and AMC to describe the memory architecture. The resulting design can be compiled to Verilog and simulated with a single command. We hope that this integration will enable a more productive design flow for hardware accelerators. ## Design Example -To use Allo with AMC, the designer only needs to write their kernel in Python. Then, then user can simply specify which Python function to build with the AMC backend. Moreover, AMC acts a drop-in replacement to the other backends in the Allo ecosystem, making functional testing and debugging seamless. In the far majority of cases, the [NumPy](https://numpy.org/) or the LLVM backend is suitable for use as a golden reference model. In this section, we walk through an example where we functionally verify a kernel built with AMC. Then, we will record some resource estimates and execution times. +To use Allo with AMC, the designer only needs to write their kernel in Python. Then, then user can simply specify which Python function to build with the AMC backend. Moreover, AMC acts as a drop-in replacement to the other backends in the Allo ecosystem, making functional testing and debugging seamless. In the far majority of cases, the [NumPy](https://numpy.org/) or the LLVM backend is suitable for use as a golden reference model. In this section, we walk through an example where we functionally verify a kernel built with AMC. Then, we will record some resource estimates and execution times. Our illustrative example will be matrix multiplication. What would ordinarily be a cumbersome task when using the vendor tools, like [Vitis HLS](https://www.xilinx.com/products/design-tools/vitis/vitis-hls.html), becomes a simple, 5 minute exercise. First, we specify some inputs initialized to random values. Then, `build()` the accelerator. Finally, we call both the software and hardware simulations and check their outputs. Compared to a C/C++ based tool flow, the amount of boilerplate code and scripting is reduced to near zero. In the end, we can represent this application with only 18 lines of code: @@ -40,9 +42,9 @@ def test_amc(): A = np.random.randint(0, 20, size=(N, N), dtype="int32") B = np.random.randint(0, 20, size=(N, N), dtype="int32") - # Our kernel is just matrix multiplication + # Our kernel is just matrix multiplication, Allo provides a primitive for this def kernel(A: int32[N, N], B: int32[N, N]) -> int32[N, N]: - return matmul(A, B) + return allo.matmul(A, B) # Build the accelerator with AMC backend s = allo.customize(kernel) @@ -57,7 +59,7 @@ def test_amc(): Additionally, we can also get an approximation of how much FPGA resources this design uses. Simply call `.get_resource_estimates()` after building: ```python - print(f.get_resource_estimates()) + print(f.get_resource_estimates()) # { # "BRAM36": 1, # "DSP": 3, @@ -150,7 +152,7 @@ def vadd(A: uint32[N], B: uint32[N]) -> uint32[N]: return A + B ``` -Outside of what is shown here, the Allo DSL allows much more elaborate kernels and control over compute customizations, like loop tiling and reuse buffers. One again, you can get more information on Allo and its MLIR dialect by reading last years blog post by [Hongzheng Chen](https://www.cs.cornell.edu/courses/cs6120/2022sp/blog/hcl-mlir/). +Outside of what is shown here, the Allo DSL allows much more elaborate kernels and control over compute customizations, like loop tiling and reuse buffers. One again, you can get more information on Allo and its MLIR dialect by reading last years blog post by [Hongzheng Chen](https://www.cs.cornell.edu/courses/cs6120/2022sp/blog/hcl-mlir/). To conclude, we hope this example demonstrates the usefulness of the Allo frontend for high-level hardware design and further development of the AMC HLS compiler. As far as we are aware, the only other frameworks using Python to drive FPGA high-level synthesis are [LeFlow](https://arxiv.org/abs/1807.05317) and [PyLog](https://ieeexplore.ieee.org/document/9591456). However, neither of these efforts are using a homebrewed HLS compiler like us. @@ -163,6 +165,34 @@ TODO(explain all the steps) ### Overview ### Allo +Allo leverages an algorithm-optimization decoupled paradigm, which means users can first define the algorithm in a high-level language and then optimize the program with various hardware customization techniques (i.e., schedule primitives). Back to the matmul example, without using the provided primitive, the code would look like this: + +```python +def matmul(A: int32[16, 16], B: int32[16, 16]) -> int32[16, 16]: + C: int32[16, 16] = 0 + for i, j, k in allo.grid(16, 16, 16): + C[i, j] += A[i, k] * B[k, j] + return C +``` + +[This blog post](https://siboehm.com/articles/22/Fast-MMM-on-CPU) describes an effective way of optimizing matrix multiplication. The key idea is to reorder and tile the loops for a better data locality. The optimized loop order would be `i, k, j`. With Allo, we can easily achieve this with just two lines of code: + +```python +schedule = allo.customize(matmul) +schedule.reorder("i", "k", "j") +``` + +Loop tiling is supported by the `split()` directive: +```python +schedule.split("i", factor=4) +``` + +Finally, we can build the design for various backends: +```python +module = schedule.build(target="llvm") # can also be 'vlhs', 'amc' +``` + +TODO: what is the most important feature of Allo for this project? ### AMC From cfdd6b41bca6ffdb7b3413c73521573e821c885d Mon Sep 17 00:00:00 2001 From: matth2k Date: Sun, 10 Dec 2023 18:51:15 -0500 Subject: [PATCH 12/29] add dependency graph --- content/2023-12-09-allo-amc/index.md | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/content/2023-12-09-allo-amc/index.md b/content/2023-12-09-allo-amc/index.md index 5fa5fd651..e96c380f7 100644 --- a/content/2023-12-09-allo-amc/index.md +++ b/content/2023-12-09-allo-amc/index.md @@ -160,7 +160,13 @@ To conclude, we hope this example demonstrates the usefulness of the Allo fronte Under the hood, the Allo frontend is automating all the interactions with other tools, IRs, and frameworks. Nonetheless, understanding each component is important to understanding the novelty in our approach. -TODO(explain all the steps) +
+Diagram of build dependencies +
+ +The top row of dependencies are C++ codebases linked together as static libraries. We enter interact with this library with input MLIR generated from Allo. On the backend, we emit Calyx which is lowered to Verilog by a separate [Calyx compiler](https://github.com/cucapra/calyx) that is written in Rust. + +The HCL dialect and passes are primarily responsible for processing the customization directives of the Allo frontend. Then, AMC and CIRCT carry out the "traditional" steps of high-level synthesis: allocation, scheduling, and binding. Finally, the Calyx compiler generates the data paths and control logic for the scheduled program. ### Overview From f9c3068af31f6df9a5c4c2d0ed994c6e509ae954 Mon Sep 17 00:00:00 2001 From: matth2k Date: Sun, 10 Dec 2023 19:20:45 -0500 Subject: [PATCH 13/29] proofread intro --- content/2023-12-09-allo-amc/index.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/content/2023-12-09-allo-amc/index.md b/content/2023-12-09-allo-amc/index.md index e96c380f7..f9e1a1aff 100644 --- a/content/2023-12-09-allo-amc/index.md +++ b/content/2023-12-09-allo-amc/index.md @@ -17,17 +17,17 @@ For our final course project, we have integrated our HLS (high-level sythesis) c ### Hardware Accelerators -Hardware accelerators have been a promising way of improving the performance and energy efficiency of compute intensive applications. However, the design effort required to create a new accelerator is often too high for the average programmer. This is because the design process requires a deep understanding of the underlying hardware architecture and the tools used to compile the design. For example, the designer must understand how to map their algorithm to the hardware, how to optimize for the target (e.g., FPGAs), and how to debug the design. Moreover, the designer must also understand the tool flow, which includes the hardware description language (HDL), the synthesis tools, and the simulation tools. In the end, the designer must be an expert in both hardware and software to create a new accelerator. As a result, bringing up a new accelerator is a slow and sometimes tedious process. +When CPU and GPU optimizations have been exhausted, custom hardware accelerators are the main option for improving the performance and energy efficiency of compute intensive applications. However, the design effort required to create a new accelerator is often too high for the average programmer. This is because the design process requires a deep understanding of the underlying hardware architecture, how it can be used, and how the CAD tools behave. For example, the designer must understand how to map their algorithm to the floorplan of the hardware and how to optimize for the functional units present in architecture (e.g., LUTs, DSPs on FPGAs). Of course, debugging is its own challenge when designing hardware. Finally, the designer also needs to battle with inadequate vendor tools, which are used to synthesize the hardware description language (HDL) and run behavioral and cycle-accurate simulations. In the end, the accelerator designer must be an expert in a very tall stack of technologies, spanning both hardware and software. As a result, bringing up a new accelerator is a slow, tedious, and typically expensive process. ### High-Level Synthesis -High-Level Synthesis (HLS) is a rising solution to the problem of hardware design productivity. The idea is to raise the level of abstraction of HDLs from the commonly-used register transfer level (RTL) to a higher-level language like C/C++. This allows the designer to focus more on the algorithm and less on the hardware details such as interfacing and timing. The core part of HLS it a compiler which infers a mapping from the high-level language to the hardware, which is often done by scheduling, resource allocation, and binding. In the end, the HLS compiler outputs RTL code to be synthesized by downstream tools. However, current HLS tools are not able to fully free designers from understanding hardware architectures. They often rely on special directives (e.g., C++ pragmas) from the designer to guide the optimization process. Sometimes, the designer must even rewrite their code to fit the HLS compiler's model of computation. +High-Level Synthesis (HLS) is one such solution to solve the problem of hardware design productivity. The general idea is to raise the level of abstraction from the commonly-used register transfer level (RTL) (e.g. Verilog) to a higher-level language like C/C++. This allows the designer to focus more at the algorithm level and less on the hardware details, such as interfaces and timing. The "magic" of HLS compilers is that it can infer a gate-level mapping from the high-level language to the underlying hardware. The main steps of generating this mapping are scheduling, resource allocation, and binding. In the end, the outputted RTL code from HLS can be synthesized by downstream tools. However, current HLS tools greatly fall short in their promise to free designers from thinking at the architecture level. They rely on special directives (e.g., C++ pragmas) from the designer to guide the optimization process. Oftentimes, the designer must even rewrite their code to fit the HLS compiler's model of computation. ### MLIR and Incubator Projects -Improving HLS with advanced compiler techniques is a very active area of research. There are many outstanding HLS tools/frameworks such as [TAPA](https://tapa.readthedocs.io/en/release/overview/overview.html), [Dynamatic](https://dynamatic.epfl.ch/), and [HeteroCL](https://heterocl.csl.cornell.edu/). However, these tools are developed independently with different compilation flows, which brings difficulties of integrating them together. [MLIR](https://mlir.llvm.org/) is a new compiler design paradigm where the source language is compiled through multiple levels of modularized intermediate representations (IRs), also known as dialects. Dialects act like domain-specific languages (DSLs) and can capture the approprate details at each level of abstraction. +Reinventing HLS with advanced compiler techniques is an active area of research. There are many outstanding HLS tools/frameworks such as [TAPA](https://tapa.readthedocs.io/en/release/overview/overview.html), [Dynamatic](https://dynamatic.epfl.ch/), and [HeteroCL](https://heterocl.csl.cornell.edu/). However, these tools are developed independently with different compilation flows, which brings difficulties of integrating them together. [MLIR](https://mlir.llvm.org/) is a new compiler design paradigm where the source language is compiled through multiple levels of modularized intermediate representations (IRs), also known as dialects. Dialects act like domain-specific languages (DSLs) and can capture the approprate details at each level of abstraction. -The [CIRCT](https://circt.llvm.org/) project proposes an MLIR-based development methodology for hardware design. It represents key components of hardware as MLIR dialects such as finite state machines (FSM), pipelines, and interface handshaking. HeteroCL has been migrated to the MLIR ecosystem as a dialect, with a new Python frontend called Allo. Allo decouples algorithm, optimization, and backend targets to enable productive hardware design and testing. Accelerator Memory Compiler (AMC) is an MLIR dialect for representing memory architecture. It captures common memory constructs such as partitioning, banking, and arbitration. AMC can be further lowered to Calyx, which is a part of the CIRCT system, and finally to synthesizable Verilog. In this project, we integrate Allo and AMC to enable a Python frontend for AMC. This allows us to use Allo to describe the algorithm and AMC to describe the memory architecture. The resulting design can be compiled to Verilog and simulated with a single command. We hope that this integration will enable a more productive design flow for hardware accelerators. +The [CIRCT](https://circt.llvm.org/) project expands the MLIR-based development methodology for hardware design. It represents key components of hardware as MLIR dialects such as finite state machines (FSM), pipelines, and interface handshaking. HeteroCL has been migrated to the MLIR ecosystem as a dialect, with a new Python frontend called Allo. Allo decouples the interactions between the algorithm, hardware optimizations, and backend targets to enable productive design and testing. Lastly, Accelerator Memory Compiler (AMC) is an MLIR dialect for representing memory architecture. Its expressiveness is able to capture common memory organization strategies such as partitioning, banking, and arbitration. AMC can be further lowered to Calyx, which is also part of the CIRCT ecosystem. Calyx IR gives us a pathway to finally to synthesizable Verilog. The contribution of this project is that we integrated Allo with AMC to enable a Python frontend for AMC. This allows us to use Allo to describe the algorithm and AMC to describe the memory architecture. The resulting design can be compiled to Verilog and simulated with a single function call. In the end, we hope that this integration will enable a more productive design flow for hardware accelerators as well as help us find more bugs in AMC. ## Design Example From a0e6fab445c434e50bcc3e09d2a0061c5ad90fce Mon Sep 17 00:00:00 2001 From: matth2k Date: Sun, 10 Dec 2023 19:43:44 -0500 Subject: [PATCH 14/29] add future work --- content/2023-12-09-allo-amc/index.md | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/content/2023-12-09-allo-amc/index.md b/content/2023-12-09-allo-amc/index.md index f9e1a1aff..5a93cc3e9 100644 --- a/content/2023-12-09-allo-amc/index.md +++ b/content/2023-12-09-allo-amc/index.md @@ -139,7 +139,7 @@ For more information on the motivation behind AMC and the dialect itself, you ca # You can now take the debugging to your favorite waveform viewer ``` -Writing other types of kernels is as easy as writing normal Python. For example, here are a handful of other kernels which are just a simple to get up and running: +Writing other types of kernels is as easy as writing normal Python. For example, here are a couple of other kernels which are just a simple to get up and running: ```python def fibonnaci(A: uint32[N]): @@ -158,7 +158,7 @@ To conclude, we hope this example demonstrates the usefulness of the Allo fronte ## Tool flow -Under the hood, the Allo frontend is automating all the interactions with other tools, IRs, and frameworks. Nonetheless, understanding each component is important to understanding the novelty in our approach. +Under the hood, the Allo frontend is automating all the interactions with other tools, IRs, and frameworks. Nonetheless, understanding the interactions of each component is important to understanding the novelty in our approach.
Diagram of build dependencies @@ -248,8 +248,12 @@ The main story here is revealed when looking at the core MLIR dialects Allo is e ## Future Work -TODO -- Fix how allow constructs affine for. Needs to Store to load forward +Given that the focus of this project was primarily the software plumbing required to get things working end-to-end, there is still a lot of work needed to increase the quality of results. Right now, there are too many ways to accidentally create a slow design that has many redundant memory operations. Moreover, some designs just don't work, exposing bugs in our scheduling pass. Here is a list of features and fixes we intend to eventually implement: + +- Fix how Allo constructs `affine.for` loops. Right now Allo is not using inter-iteration arguments, meaning the data flow between loop iterations is through memory reads and writes. This is much slower, because it artificially increases the II of the pipeline. +- Handle scalar values. Allo creates a memref cell to hold scalar values, and this once again limits performance. Every interaction with the variable is with loads and stores, instead of doing the proper SSA conversion. +- Fix scheduler bugs. +- Use Allo customization directives to assist AMC in inferring more efficient scratchpad memories. For example, array partitioning and memory access patterns are hints that Allo could provide to our allocation pass. ## Conclusion From cf80385816ae81356c75c5f9a8b9f305cdf09593 Mon Sep 17 00:00:00 2001 From: matth2k Date: Sun, 10 Dec 2023 19:47:54 -0500 Subject: [PATCH 15/29] add tool flow image --- .../2023-12-09-allo-amc/allo_dependencies.png | Bin 0 -> 30567 bytes content/2023-12-09-allo-amc/index.md | 30 +++++++++++++++--- 2 files changed, 26 insertions(+), 4 deletions(-) create mode 100644 content/2023-12-09-allo-amc/allo_dependencies.png diff --git a/content/2023-12-09-allo-amc/allo_dependencies.png b/content/2023-12-09-allo-amc/allo_dependencies.png new file mode 100644 index 0000000000000000000000000000000000000000..643dc6e2909f20fa1b503ee925c6d723ee3028c4 GIT binary patch literal 30567 zcmeFZXH-*L)F>MDC`S=E9t#QrDosH^snYeJVn9Ht(ovdp34|U%QLq6@l^S|4(xpbF z*Fb;(p(zjogb)cNAqh$Dj^}>w&%3Yuc;6fEzWePl_So5buRYhAbFJCu%9{sgwSiSovSRVSLl=EgvDkG>JC+gn8vyo#^t` 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z$HfdP5Z9^-nJGP^Oz=H!T^JzAP{FMgFkvH%K=-27Xdq_-qhC0k=pA)TpKw(bAr2FJBffNd}T zo0R|UzuR5@&(c=^-34>v(O((;|D*N)|Kk740sAO_CO#py-FoidOh4aDDR405>3?|1 z{pv1?>K+cDmiv^dZ6xsD)4KC(9Tru_=J+$ToO#~*H#FZZ1mQN57?VX!jrbnN^%daQ z7J+VceC)-oF>l>GfS!G$C0=$v8tv*bcLlh^i(^Ca|M53_cac}1+3a?lg68p1)XKTS zzE?~H^UPNN%~I%iT~}8Zi4I))vo`fZFZTEpCUqB~|9wIn@Taf!$Fu +```mlir + amc.memory @amcMemory0(!amc.dynamic_port<256xi32, w>, !amc.dynamic_port<128xi32, r>, !amc.dynamic_port<128xi32, r>) { + %0 = amc.alloc : !amc.memref<256xi32> + %1 = amc.create_port(%0 : !amc.memref<256xi32>) : !amc.dynamic_port<256xi32, w> + %2 = amc.create_port(%0 : !amc.memref<256xi32>) : !amc.dynamic_port<256xi32, r> + amc.extern %1, %2, %2 : !amc.dynamic_port<256xi32, w>, !amc.dynamic_port<256xi32, r>, !amc.dynamic_port<256xi32, r> + } + func.func @main(%arg0: memref<256xi32>, %arg1: memref<256xi32>, %arg2: memref<256xi32>) { + %0:3 = amc.inst @amcMemory0_inst of @amcMemory0 : !amc.dynamic_port<256xi32, w>, !amc.dynamic_port<256xi32, r>, + !amc.dynamic_port<256xi32, r> + // Buffer data into a scratchpad + affine.for %arg3 = 0 to 256 { + %1 = affine.load %arg0[%arg3] : memref<256xi32> + amc.affine_store %1, %0#0[%arg3] : !amc.dynamic_port<256xi32, w> + } + // Split data into two separate outputs + affine.for %arg3 = 0 to 128 { + %1 = amc.affine_load %0#1[%arg3] : !amc.dynamic_port<256xi32, r> + %2 = amc.affine_load %0#2[%arg3 + 128] : !amc.dynamic_port<256xi32, r> + affine.store %1, %arg1[%arg3] : memref<128xi32> + affine.store %2, %arg2[%arg3 + 128] : memref<128xi32> + } + return + } +``` The following diagram shows the full pass pipeline of compiling the core MLIR dialects to Verilog: From 8a5a9a171529f98c652f635bd1e6fddbbd550677 Mon Sep 17 00:00:00 2001 From: matth2k Date: Sun, 10 Dec 2023 20:00:47 -0500 Subject: [PATCH 16/29] fix some formatting issues --- content/2023-12-09-allo-amc/index.md | 31 +++++++++------------------- 1 file changed, 10 insertions(+), 21 deletions(-) diff --git a/content/2023-12-09-allo-amc/index.md b/content/2023-12-09-allo-amc/index.md index 61802c186..2c67c3671 100644 --- a/content/2023-12-09-allo-amc/index.md +++ b/content/2023-12-09-allo-amc/index.md @@ -42,7 +42,8 @@ def test_amc(): A = np.random.randint(0, 20, size=(N, N), dtype="int32") B = np.random.randint(0, 20, size=(N, N), dtype="int32") - # Our kernel is just matrix multiplication, Allo provides a primitive for this + # Our kernel is just matrix multiplication + # Allo provides a primitive for this def kernel(A: int32[N, N], B: int32[N, N]) -> int32[N, N]: return allo.matmul(A, B) @@ -161,7 +162,7 @@ To conclude, we hope this example demonstrates the usefulness of the Allo fronte Under the hood, the Allo frontend is automating all the interactions with other tools, IRs, and frameworks. Nonetheless, understanding the interactions of each component is important to understanding the novelty in our approach.

-Diagram of build dependencies +Diagram of build dependencies
The top row of dependencies are C++ codebases linked together as static libraries. We enter interact with this library with input MLIR generated from Allo. On the backend, we emit Calyx which is lowered to Verilog by a separate [Calyx compiler](https://github.com/cucapra/calyx) that is written in Rust. @@ -204,7 +205,7 @@ TODO: what is the most important feature of Allo for this project? AMC (Accelerator Memory Compiler) is an entirely new plane of intermediate representation dedicated to representing memory architecture. To explain the need for such a dialect, the current state of conventional high-level synthesis compilers must be understood. As a brief summary, current HLS tools lacks an expressive model of memory, and it takes great manual effort to unlock the power of spatial architectures. This is by and large a consequence of the chosen source language. Most HLS compilers have a C/C++ frontend and LLVM middle end. As a consequence, every HLS compiler also has a set of compiler directives (`#pragma`'s) to fill in the semantic gaps of compiling to spatial hardware. For example, there are pragmas for partitioning memories, instantiating FIFOs, loop pipelining, and much more. By not having first class constructs for these design elements, optimization becomes tightly-coupled with source rewrites and HLS falls flat on its promises of high productivity. For the interested reader, we think this [blog post](https://specbranch.com/posts/fpgas-what-happened/) helps explain the current state of the FPGA accelerators for outsiders. -Back to AMC, the custom dialect elaborates the *real* limiting resources of memory on spatial architectures: the ports. Each embedded block RAM on the FPGA has only two ports, and it takes an intelligent design methodology to utilize these memories in such a way that maximizes performance. AMC eliminates the guessing game by elaborating the description of the memory subsystem and optimizing it for the program at hand. To accompany the AMC dialect, we use [Calyx IR](https://calyxir.org/) to represent the control logic of the scheduled program. Here is a very simple program allocated with an AMC memory: +Back to AMC, the custom dialect elaborates the *real* limiting resources of memory on spatial architectures: the ports. Each embedded block RAM on the FPGA has only two ports, and it takes an intelligent design methodology to utilize these memories in such a way that maximizes performance. AMC eliminates the guessing game by elaborating the description of the memory subsystem and optimizing it for the program at hand. To accompany the AMC dialect, we use [Calyx IR](https://calyxir.org/) to represent the control logic of the scheduled program. Here is a very simple program allocated with a high-level AMC memory: ```mlir amc.memory @amcMemory0(!amc.dynamic_port<256xi32, w>, !amc.dynamic_port<128xi32, r>, !amc.dynamic_port<128xi32, r>) { @@ -213,29 +214,14 @@ Back to AMC, the custom dialect elaborates the *real* limiting resources of memo %2 = amc.create_port(%0 : !amc.memref<256xi32>) : !amc.dynamic_port<256xi32, r> amc.extern %1, %2, %2 : !amc.dynamic_port<256xi32, w>, !amc.dynamic_port<256xi32, r>, !amc.dynamic_port<256xi32, r> } - func.func @main(%arg0: memref<256xi32>, %arg1: memref<256xi32>, %arg2: memref<256xi32>) { - %0:3 = amc.inst @amcMemory0_inst of @amcMemory0 : !amc.dynamic_port<256xi32, w>, !amc.dynamic_port<256xi32, r>, - !amc.dynamic_port<256xi32, r> - // Buffer data into a scratchpad - affine.for %arg3 = 0 to 256 { - %1 = affine.load %arg0[%arg3] : memref<256xi32> - amc.affine_store %1, %0#0[%arg3] : !amc.dynamic_port<256xi32, w> - } - // Split data into two separate outputs - affine.for %arg3 = 0 to 128 { - %1 = amc.affine_load %0#1[%arg3] : !amc.dynamic_port<256xi32, r> - %2 = amc.affine_load %0#2[%arg3 + 128] : !amc.dynamic_port<256xi32, r> - affine.store %1, %arg1[%arg3] : memref<128xi32> - affine.store %2, %arg2[%arg3 + 128] : memref<128xi32> - } - return - } ``` +The role of the AMC compiler is to take in a high-level description of memory organization and figure out how to best compile it to the target architecture. It accounts for some of the properties of ... TODO finish. + The following diagram shows the full pass pipeline of compiling the core MLIR dialects to Verilog:
-Diagram for AMC pass pipeline +Diagram for AMC pass pipeline
## Results @@ -243,6 +229,7 @@ The following diagram shows the full pass pipeline of compiling the core MLIR di In this section, we report the latency and resource measures of a select set of micro-benchmarks. By using small testcases, we have the best chance of understanding how the high-level constructs are being mapped to hardware and where the compiler inefficiencies lie. With that said, here are a table of benchmarks compiled with our toolflow versus Vitis C HLS. **AMC** + | Benchmark | Latency (Cycles) | LUTs | FFs | BRAM36s | DSPs | | ------------- | ---------------- | ---- | --- | ------- | ---- | | matmul16x16 | 15016 | 467 | 255 | 1 | 3 | @@ -251,6 +238,7 @@ In this section, we report the latency and resource measures of a select set of | fibonacci20 | 77 | 120 | 151 | 0 | 0 | **Vitis 2022** + | Benchmark | Latency (Cycles) | LUTs | FFs | BRAM36s | DSPs | | ------------- | ---------------- | ---- | --- | ------- | ---- | | matmul16x16 | 5409 | 221 | 74 | 0 | 3 | @@ -259,6 +247,7 @@ In this section, we report the latency and resource measures of a select set of | fibonacci20 | 41 | 226 | 50 | 0 | 0 | **Difference: AMC - Vitis** + | Benchmark | Latency (Cycles) | LUTs | FFs | BRAM36s | DSPs | | ------------- | ---------------- | ----- | ------ | ------- | ----- | | matmul16x16 | +170% | +110% | +240% | - | +0% | From 751942f82f3a84a94bfdc6e95762ad6e550423c6 Mon Sep 17 00:00:00 2001 From: Yixiao Du Date: Sun, 10 Dec 2023 20:56:20 -0500 Subject: [PATCH 17/29] add overview figure --- content/2023-12-09-allo-amc/index.md | 3 +++ content/2023-12-09-allo-amc/overview.svg | 1 + 2 files changed, 4 insertions(+) create mode 100644 content/2023-12-09-allo-amc/overview.svg diff --git a/content/2023-12-09-allo-amc/index.md b/content/2023-12-09-allo-amc/index.md index 2c67c3671..274fb8d5f 100644 --- a/content/2023-12-09-allo-amc/index.md +++ b/content/2023-12-09-allo-amc/index.md @@ -14,6 +14,9 @@ name = "Yixiao Du" ## Introduction For our final course project, we have integrated our HLS (high-level sythesis) compiler, AMC, with a Python frontend, called Allo. In the end, we are able to compile and simulate custom hardware designs with extremely concise design descriptions and short compile times. As a consequence, we greatly reduce the design effort required for new accelerators as well as offer a convenient tool for functional verification. In this report, we walk through an example design with our tool flow, offer insight into how the underlying compiler works, and finally evaluate some benchmarks with latency and resource utilization measurements. +
+Project Overview +
### Hardware Accelerators diff --git a/content/2023-12-09-allo-amc/overview.svg b/content/2023-12-09-allo-amc/overview.svg new file mode 100644 index 000000000..52c392fdd --- /dev/null +++ b/content/2023-12-09-allo-amc/overview.svg @@ -0,0 +1 @@ +
design.py
design.py
Hardware
Hardware
Testbench
Testbench
Allo
Allo
AMC
AMC
Calyx
CalyxText is not SVG - cannot display \ No newline at end of file From fb23a22e57b353b7ea602f6c8ac9dd2339a23827 Mon Sep 17 00:00:00 2001 From: matth2k Date: Sun, 10 Dec 2023 22:34:36 -0500 Subject: [PATCH 18/29] address TODO comments --- content/2023-12-09-allo-amc/index.md | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/content/2023-12-09-allo-amc/index.md b/content/2023-12-09-allo-amc/index.md index 274fb8d5f..8674817e5 100644 --- a/content/2023-12-09-allo-amc/index.md +++ b/content/2023-12-09-allo-amc/index.md @@ -185,7 +185,7 @@ def matmul(A: int32[16, 16], B: int32[16, 16]) -> int32[16, 16]: return C ``` -[This blog post](https://siboehm.com/articles/22/Fast-MMM-on-CPU) describes an effective way of optimizing matrix multiplication. The key idea is to reorder and tile the loops for a better data locality. The optimized loop order would be `i, k, j`. With Allo, we can easily achieve this with just two lines of code: +[This blog post](https://siboehm.com/articles/22/Fast-MMM-on-CPU) elaborates effective ways of optimizing matrix multiplication, which can be replicated in Allo. The key idea is to reorder and tile the loops for better data locality. The optimized loop ordering would be `i, k, j`. With Allo, we can easily achieve this with just two lines of code: ```python schedule = allo.customize(matmul) @@ -202,7 +202,7 @@ Finally, we can build the design for various backends: module = schedule.build(target="llvm") # can also be 'vlhs', 'amc' ``` -TODO: what is the most important feature of Allo for this project? +This is just one example of compute customizations with Allo, and there are several other hardware customization primitives that will play to AMC's strengths. We believe that with some additional work the Allo frotnend can provides hints for AMC to better infer FIFO streams, partitioned arrays, and banked memories. Such memory customizations will allow for more elaborate parallelization schemes, and ultimately we expect speedups that will beat the commercial tools. ### AMC @@ -219,9 +219,7 @@ Back to AMC, the custom dialect elaborates the *real* limiting resources of memo } ``` -The role of the AMC compiler is to take in a high-level description of memory organization and figure out how to best compile it to the target architecture. It accounts for some of the properties of ... TODO finish. - -The following diagram shows the full pass pipeline of compiling the core MLIR dialects to Verilog: +The role of the AMC compiler is to take in a high-level description of memory organization (as seen above) and figure out how to best compile it to the target architecture. It accounts for some of the properties of underlying architecture, like BRAM size and port count, as well as the context in which the memory is being used. It is a very gradual lowering process, and the explanation of the whole pass pipeline won't even start to fit in this post. However, the following diagram may offer a rough idea of how the core MLIR and AMC dialects to Verilog:
Diagram for AMC pass pipeline @@ -271,4 +269,6 @@ Given that the focus of this project was primarily the software plumbing require ## Conclusion -The project was by and large a success, because we have achieved a much higher level of automation in evaluating the AMC+Calyx toolflow. Being able to write HLS kernels with `numpy` and run the RTL simulation as a normal function call greatly reduces the amount of effort in adding a new test case. Moreover, the `.dump_vcd()` and `.get_resource_estimates()` provide more tools for debugging without having to manually interact with the synthesis tools. \ No newline at end of file +The project was by and large a success, because we have achieved a much higher level of automation in evaluating the AMC+Calyx toolflow. Being able to write HLS kernels with `numpy` and run the RTL simulation as a normal function call greatly reduces the amount of effort in adding test cases. Moreover, the `.dump_vcd()` and `.get_resource_estimates()` provide more tools for debugging without having to manually interact with the synthesis tools. We are optimistic that having Allo as a frontend will accelerate the development of AMC. + +Both Allo and AMC are ongoing developments that are not ready to be open sourced. However, [the HCL dialect](https://github.com/cornell-zhang/hcl-dialect), [CIRCT](https://github.com/llvm/circt), and [Calyx](https://github.com/cucapra/calyx) all have public GitHub repositories. \ No newline at end of file From 6efeeb0557a6eafa57994823f33dcc051c90a1cf Mon Sep 17 00:00:00 2001 From: matth2k Date: Sun, 10 Dec 2023 22:39:48 -0500 Subject: [PATCH 19/29] giv eHongzheng shoutout --- content/2023-12-09-allo-amc/index.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/content/2023-12-09-allo-amc/index.md b/content/2023-12-09-allo-amc/index.md index 8674817e5..9fbb9481c 100644 --- a/content/2023-12-09-allo-amc/index.md +++ b/content/2023-12-09-allo-amc/index.md @@ -271,4 +271,4 @@ Given that the focus of this project was primarily the software plumbing require The project was by and large a success, because we have achieved a much higher level of automation in evaluating the AMC+Calyx toolflow. Being able to write HLS kernels with `numpy` and run the RTL simulation as a normal function call greatly reduces the amount of effort in adding test cases. Moreover, the `.dump_vcd()` and `.get_resource_estimates()` provide more tools for debugging without having to manually interact with the synthesis tools. We are optimistic that having Allo as a frontend will accelerate the development of AMC. -Both Allo and AMC are ongoing developments that are not ready to be open sourced. However, [the HCL dialect](https://github.com/cornell-zhang/hcl-dialect), [CIRCT](https://github.com/llvm/circt), and [Calyx](https://github.com/cucapra/calyx) all have public GitHub repositories. \ No newline at end of file +Both Allo and AMC are ongoing developments that are not ready to be open sourced. However, [the HCL dialect](https://github.com/cornell-zhang/hcl-dialect), [CIRCT](https://github.com/llvm/circt), and [Calyx](https://github.com/cucapra/calyx) all have public GitHub repositories. Finally, we want to thank [Hongzheng](https://www.linkedin.com/in/hongzheng-chen/en) for helping familiarize us with his Allo work. \ No newline at end of file From 75be3350cf837121e6659da8bffce0344ebeb2c5 Mon Sep 17 00:00:00 2001 From: matth2k Date: Sun, 10 Dec 2023 22:43:50 -0500 Subject: [PATCH 20/29] move post to right dir --- .../2023-12-09-allo-amc/allo_dependencies.png | Bin .../{ => blog}/2023-12-09-allo-amc/amc_passes.png | Bin content/{ => blog}/2023-12-09-allo-amc/index.md | 0 content/{ => blog}/2023-12-09-allo-amc/overview.svg | 0 4 files changed, 0 insertions(+), 0 deletions(-) rename content/{ => blog}/2023-12-09-allo-amc/allo_dependencies.png (100%) rename content/{ => blog}/2023-12-09-allo-amc/amc_passes.png (100%) rename content/{ => blog}/2023-12-09-allo-amc/index.md (100%) rename content/{ => blog}/2023-12-09-allo-amc/overview.svg (100%) diff --git a/content/2023-12-09-allo-amc/allo_dependencies.png b/content/blog/2023-12-09-allo-amc/allo_dependencies.png similarity index 100% rename from content/2023-12-09-allo-amc/allo_dependencies.png rename to content/blog/2023-12-09-allo-amc/allo_dependencies.png diff --git a/content/2023-12-09-allo-amc/amc_passes.png b/content/blog/2023-12-09-allo-amc/amc_passes.png similarity index 100% rename from content/2023-12-09-allo-amc/amc_passes.png rename to content/blog/2023-12-09-allo-amc/amc_passes.png diff --git a/content/2023-12-09-allo-amc/index.md b/content/blog/2023-12-09-allo-amc/index.md similarity index 100% rename from content/2023-12-09-allo-amc/index.md rename to content/blog/2023-12-09-allo-amc/index.md diff --git a/content/2023-12-09-allo-amc/overview.svg b/content/blog/2023-12-09-allo-amc/overview.svg similarity index 100% rename from content/2023-12-09-allo-amc/overview.svg rename to content/blog/2023-12-09-allo-amc/overview.svg From 7d37730a0b62736df62c45f0be8ed6fb68eb3347 Mon Sep 17 00:00:00 2001 From: matth2k Date: Sun, 10 Dec 2023 22:49:01 -0500 Subject: [PATCH 21/29] make title not wrap --- content/blog/2023-12-09-allo-amc/index.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/content/blog/2023-12-09-allo-amc/index.md b/content/blog/2023-12-09-allo-amc/index.md index 9fbb9481c..b682d8809 100644 --- a/content/blog/2023-12-09-allo-amc/index.md +++ b/content/blog/2023-12-09-allo-amc/index.md @@ -1,5 +1,5 @@ +++ -title = "Frontend Integration for AMC (Accelerator Memory Compiler)" +title = "Frontend Integration for Accelerator Memory Compiler" [extra] bio = """ Matthew Hofmann is a 2nd year Ph.D. student researching design automation for reconfigurable hardware.
From 3fd08a09c12e991ecb9efcf4a97dcf059c6ab293 Mon Sep 17 00:00:00 2001 From: matth2k Date: Tue, 12 Dec 2023 18:23:46 -0500 Subject: [PATCH 22/29] rename frontend --- ..._dependencies.png => hcl_dependencies.png} | Bin content/blog/2023-12-09-allo-amc/index.md | 65 +++++++----------- 2 files changed, 25 insertions(+), 40 deletions(-) rename content/blog/2023-12-09-allo-amc/{allo_dependencies.png => hcl_dependencies.png} (100%) diff --git a/content/blog/2023-12-09-allo-amc/allo_dependencies.png b/content/blog/2023-12-09-allo-amc/hcl_dependencies.png similarity index 100% rename from content/blog/2023-12-09-allo-amc/allo_dependencies.png rename to content/blog/2023-12-09-allo-amc/hcl_dependencies.png diff --git a/content/blog/2023-12-09-allo-amc/index.md b/content/blog/2023-12-09-allo-amc/index.md index b682d8809..75021d90b 100644 --- a/content/blog/2023-12-09-allo-amc/index.md +++ b/content/blog/2023-12-09-allo-amc/index.md @@ -13,7 +13,7 @@ name = "Yixiao Du" ## Introduction -For our final course project, we have integrated our HLS (high-level sythesis) compiler, AMC, with a Python frontend, called Allo. In the end, we are able to compile and simulate custom hardware designs with extremely concise design descriptions and short compile times. As a consequence, we greatly reduce the design effort required for new accelerators as well as offer a convenient tool for functional verification. In this report, we walk through an example design with our tool flow, offer insight into how the underlying compiler works, and finally evaluate some benchmarks with latency and resource utilization measurements. +For our final course project, we have integrated our HLS (high-level sythesis) compiler, AMC, with a Python frontend, called HCL. In the end, we are able to compile and simulate custom hardware designs with extremely concise design descriptions and short compile times. As a consequence, we greatly reduce the design effort required for new accelerators as well as offer a convenient tool for functional verification. In this report, we walk through an example design with our tool flow, offer insight into how the underlying compiler works, and finally evaluate some benchmarks with latency and resource utilization measurements.
Project Overview
@@ -30,11 +30,11 @@ High-Level Synthesis (HLS) is one such solution to solve the problem of hardware Reinventing HLS with advanced compiler techniques is an active area of research. There are many outstanding HLS tools/frameworks such as [TAPA](https://tapa.readthedocs.io/en/release/overview/overview.html), [Dynamatic](https://dynamatic.epfl.ch/), and [HeteroCL](https://heterocl.csl.cornell.edu/). However, these tools are developed independently with different compilation flows, which brings difficulties of integrating them together. [MLIR](https://mlir.llvm.org/) is a new compiler design paradigm where the source language is compiled through multiple levels of modularized intermediate representations (IRs), also known as dialects. Dialects act like domain-specific languages (DSLs) and can capture the approprate details at each level of abstraction. -The [CIRCT](https://circt.llvm.org/) project expands the MLIR-based development methodology for hardware design. It represents key components of hardware as MLIR dialects such as finite state machines (FSM), pipelines, and interface handshaking. HeteroCL has been migrated to the MLIR ecosystem as a dialect, with a new Python frontend called Allo. Allo decouples the interactions between the algorithm, hardware optimizations, and backend targets to enable productive design and testing. Lastly, Accelerator Memory Compiler (AMC) is an MLIR dialect for representing memory architecture. Its expressiveness is able to capture common memory organization strategies such as partitioning, banking, and arbitration. AMC can be further lowered to Calyx, which is also part of the CIRCT ecosystem. Calyx IR gives us a pathway to finally to synthesizable Verilog. The contribution of this project is that we integrated Allo with AMC to enable a Python frontend for AMC. This allows us to use Allo to describe the algorithm and AMC to describe the memory architecture. The resulting design can be compiled to Verilog and simulated with a single function call. In the end, we hope that this integration will enable a more productive design flow for hardware accelerators as well as help us find more bugs in AMC. +The [CIRCT](https://circt.llvm.org/) project expands the MLIR-based development methodology for hardware design. It represents key components of hardware as MLIR dialects such as finite state machines (FSM), pipelines, and interface handshaking. HeteroCL has been migrated to the MLIR ecosystem as a dialect, with a new Python frontend called HCL. HCL decouples the interactions between the algorithm, hardware optimizations, and backend targets to enable productive design and testing. Lastly, Accelerator Memory Compiler (AMC) is an MLIR dialect for representing memory architecture. Its expressiveness is able to capture common memory organization strategies such as partitioning, banking, and arbitration. AMC can be further lowered to Calyx, which is also part of the CIRCT ecosystem. Calyx IR gives us a pathway to finally to synthesizable Verilog. The contribution of this project is that we integrated HCL with AMC to enable a Python frontend for AMC. This allows us to use HCL to describe the algorithm and AMC to describe the memory architecture. The resulting design can be compiled to Verilog and simulated with a single function call. In the end, we hope that this integration will enable a more productive design flow for hardware accelerators as well as help us find more bugs in AMC. ## Design Example -To use Allo with AMC, the designer only needs to write their kernel in Python. Then, then user can simply specify which Python function to build with the AMC backend. Moreover, AMC acts as a drop-in replacement to the other backends in the Allo ecosystem, making functional testing and debugging seamless. In the far majority of cases, the [NumPy](https://numpy.org/) or the LLVM backend is suitable for use as a golden reference model. In this section, we walk through an example where we functionally verify a kernel built with AMC. Then, we will record some resource estimates and execution times. +To use HCL with AMC, the designer only needs to write their kernel in Python. Then, then user can simply specify which Python function to build with the AMC backend. Moreover, AMC acts as a drop-in replacement to the other backends in the HCL ecosystem, making functional testing and debugging seamless. In the far majority of cases, the [NumPy](https://numpy.org/) or the LLVM backend is suitable for use as a golden reference model. In this section, we walk through an example where we functionally verify a kernel built with AMC. Then, we will record some resource estimates and execution times. Our illustrative example will be matrix multiplication. What would ordinarily be a cumbersome task when using the vendor tools, like [Vitis HLS](https://www.xilinx.com/products/design-tools/vitis/vitis-hls.html), becomes a simple, 5 minute exercise. First, we specify some inputs initialized to random values. Then, `build()` the accelerator. Finally, we call both the software and hardware simulations and check their outputs. Compared to a C/C++ based tool flow, the amount of boilerplate code and scripting is reduced to near zero. In the end, we can represent this application with only 18 lines of code: @@ -46,18 +46,18 @@ def test_amc(): B = np.random.randint(0, 20, size=(N, N), dtype="int32") # Our kernel is just matrix multiplication - # Allo provides a primitive for this + # HCL provides a primitive for this def kernel(A: int32[N, N], B: int32[N, N]) -> int32[N, N]: - return allo.matmul(A, B) + return matmul(A, B) # Build the accelerator with AMC backend - s = allo.customize(kernel) + s = customize(kernel) f = s.build(target="amc") # Run the software simulation by invoking directly np_out = kernel(A, B) # Now run the hardware simulation with AMC - allo_out = f(A, B) - np.testing.assert_array_equal(allo_out, np_out) + hcl_out = f(A, B) + np.testing.assert_array_equal(hcl_out, np_out) ``` Additionally, we can also get an approximation of how much FPGA resources this design uses. Simply call `.get_resource_estimates()` after building: @@ -156,53 +156,38 @@ def vadd(A: uint32[N], B: uint32[N]) -> uint32[N]: return A + B ``` -Outside of what is shown here, the Allo DSL allows much more elaborate kernels and control over compute customizations, like loop tiling and reuse buffers. One again, you can get more information on Allo and its MLIR dialect by reading last years blog post by [Hongzheng Chen](https://www.cs.cornell.edu/courses/cs6120/2022sp/blog/hcl-mlir/). +Outside of what is shown here, the HCL DSL allows much more elaborate kernels and control over compute customizations, like loop tiling and reuse buffers. One again, you can get more information on HCL and its MLIR dialect by reading last years blog post by [Hongzheng Chen](https://www.cs.cornell.edu/courses/cs6120/2022sp/blog/hcl-mlir/). -To conclude, we hope this example demonstrates the usefulness of the Allo frontend for high-level hardware design and further development of the AMC HLS compiler. As far as we are aware, the only other frameworks using Python to drive FPGA high-level synthesis are [LeFlow](https://arxiv.org/abs/1807.05317) and [PyLog](https://ieeexplore.ieee.org/document/9591456). However, neither of these efforts are using a homebrewed HLS compiler like us. +To conclude, we hope this example demonstrates the usefulness of the HCL frontend for high-level hardware design and further development of the AMC HLS compiler. As far as we are aware, the only other frameworks using Python to drive FPGA high-level synthesis are [LeFlow](https://arxiv.org/abs/1807.05317) and [PyLog](https://ieeexplore.ieee.org/document/9591456). However, neither of these efforts are using a homebrewed HLS compiler like us. ## Tool flow -Under the hood, the Allo frontend is automating all the interactions with other tools, IRs, and frameworks. Nonetheless, understanding the interactions of each component is important to understanding the novelty in our approach. +Under the hood, the HCL frontend is automating all the interactions with other tools, IRs, and frameworks. Nonetheless, understanding the interactions of each component is important to understanding the novelty in our approach.
-Diagram of build dependencies +Diagram of build dependencies
-The top row of dependencies are C++ codebases linked together as static libraries. We enter interact with this library with input MLIR generated from Allo. On the backend, we emit Calyx which is lowered to Verilog by a separate [Calyx compiler](https://github.com/cucapra/calyx) that is written in Rust. +The top row of dependencies are C++ codebases linked together as static libraries. We enter this library with input MLIR generated from HCL. On the backend, we emit Calyx which is lowered to Verilog by a separate [Calyx compiler](https://github.com/cucapra/calyx) that is written in Rust. -The HCL dialect and passes are primarily responsible for processing the customization directives of the Allo frontend. Then, AMC and CIRCT carry out the "traditional" steps of high-level synthesis: allocation, scheduling, and binding. Finally, the Calyx compiler generates the data paths and control logic for the scheduled program. +The HCL dialect and passes are primarily responsible for processing the customization directives of the HCL frontend. Then, AMC and CIRCT carry out the "traditional" steps of high-level synthesis: allocation, scheduling, and binding. Finally, the Calyx compiler generates the data paths and control logic for the scheduled program. ### Overview -### Allo -Allo leverages an algorithm-optimization decoupled paradigm, which means users can first define the algorithm in a high-level language and then optimize the program with various hardware customization techniques (i.e., schedule primitives). Back to the matmul example, without using the provided primitive, the code would look like this: +### HCL +HCL leverages an algorithm-optimization decoupled paradigm, which means users can first define the algorithm in a high-level language and then optimize the program with various hardware customization techniques (i.e., schedule primitives). Back to the matmul example, without using the provided primitive, the code would look like this: ```python def matmul(A: int32[16, 16], B: int32[16, 16]) -> int32[16, 16]: C: int32[16, 16] = 0 - for i, j, k in allo.grid(16, 16, 16): + for i, j, k in grid(16, 16, 16): C[i, j] += A[i, k] * B[k, j] return C ``` -[This blog post](https://siboehm.com/articles/22/Fast-MMM-on-CPU) elaborates effective ways of optimizing matrix multiplication, which can be replicated in Allo. The key idea is to reorder and tile the loops for better data locality. The optimized loop ordering would be `i, k, j`. With Allo, we can easily achieve this with just two lines of code: +[This blog post](https://siboehm.com/articles/22/Fast-MMM-on-CPU) elaborates effective ways of optimizing matrix multiplication, which can be replicated in HCL. The key idea is to reorder and tile the loops for better data locality. The optimized loop ordering would be `i, k, j`. -```python -schedule = allo.customize(matmul) -schedule.reorder("i", "k", "j") -``` - -Loop tiling is supported by the `split()` directive: -```python -schedule.split("i", factor=4) -``` - -Finally, we can build the design for various backends: -```python -module = schedule.build(target="llvm") # can also be 'vlhs', 'amc' -``` - -This is just one example of compute customizations with Allo, and there are several other hardware customization primitives that will play to AMC's strengths. We believe that with some additional work the Allo frotnend can provides hints for AMC to better infer FIFO streams, partitioned arrays, and banked memories. Such memory customizations will allow for more elaborate parallelization schemes, and ultimately we expect speedups that will beat the commercial tools. +This is just one example of compute customizations with HCL, and there are several other hardware customization primitives that will play to AMC's strengths. We believe that with some additional work the HCL frotnend can provides hints for AMC to better infer FIFO streams, partitioned arrays, and banked memories. Such memory customizations will allow for more elaborate parallelization schemes, and ultimately we expect speedups that will beat the commercial tools. ### AMC @@ -256,19 +241,19 @@ In this section, we report the latency and resource measures of a select set of | vadd20 | +410% | +760% | +2200% | - | -300% | | fibonacci20 | +88% | -47% | +200% | - | - | -The main story here is revealed when looking at the core MLIR dialects Allo is emitting after parsing the AST. Inefficiencies in how Allo infers data types and creates `affine.for` loop nests is creating way too many redundant memory operations. For example, Allo is not using store-to-load forwarding between loop iterations. Even worse, Allo tries to explicity infer data type conversions when using operations that change the data width (e.g. 32b + 32b = 33b). This for some reason is causing extra memory copy loops to convert an entire memory before it is used. We anticipate that fixing the Allo frontend to produce higher-quality loops will take some time, as it depends on some level of memory dependence analysis. Nonetheless, it will be a very important improvement to make in order to reach similar latencies as what Vitis can produce with C code. +The main story here is revealed when looking at the core MLIR dialects HCL is emitting after parsing the AST. Inefficiencies in how HCL infers data types and creates `affine.for` loop nests is creating way too many redundant memory operations. For example, HCL is not using store-to-load forwarding between loop iterations. Even worse, HCL tries to explicity infer data type conversions when using operations that change the data width (e.g. 32b + 32b = 33b). This for some reason is causing extra memory copy loops to convert an entire memory before it is used. We anticipate that fixing the HCL frontend to produce higher-quality loops will take some time, as it depends on some level of memory dependence analysis. Nonetheless, it will be a very important improvement to make in order to reach similar latencies as what Vitis can produce with C code. ## Future Work Given that the focus of this project was primarily the software plumbing required to get things working end-to-end, there is still a lot of work needed to increase the quality of results. Right now, there are too many ways to accidentally create a slow design that has many redundant memory operations. Moreover, some designs just don't work, exposing bugs in our scheduling pass. Here is a list of features and fixes we intend to eventually implement: -- Fix how Allo constructs `affine.for` loops. Right now Allo is not using inter-iteration arguments, meaning the data flow between loop iterations is through memory reads and writes. This is much slower, because it artificially increases the II of the pipeline. -- Handle scalar values. Allo creates a memref cell to hold scalar values, and this once again limits performance. Every interaction with the variable is with loads and stores, instead of doing the proper SSA conversion. +- Fix how HCL constructs `affine.for` loops. Right now HCL is not using inter-iteration arguments, meaning the data flow between loop iterations is through memory reads and writes. This is much slower, because it artificially increases the II of the pipeline. +- Handle scalar values. HCL creates a memref cell to hold scalar values, and this once again limits performance. Every interaction with the variable is with loads and stores, instead of doing the proper SSA conversion. - Fix scheduler bugs. -- Use Allo customization directives to assist AMC in inferring more efficient scratchpad memories. For example, array partitioning and memory access patterns are hints that Allo could provide to our allocation pass. +- Use HCL customization directives to assist AMC in inferring more efficient scratchpad memories. For example, array partitioning and memory access patterns are hints that HCL could provide to our allocation pass. ## Conclusion -The project was by and large a success, because we have achieved a much higher level of automation in evaluating the AMC+Calyx toolflow. Being able to write HLS kernels with `numpy` and run the RTL simulation as a normal function call greatly reduces the amount of effort in adding test cases. Moreover, the `.dump_vcd()` and `.get_resource_estimates()` provide more tools for debugging without having to manually interact with the synthesis tools. We are optimistic that having Allo as a frontend will accelerate the development of AMC. +The project was by and large a success, because we have achieved a much higher level of automation in evaluating the AMC+Calyx toolflow. Being able to write HLS kernels with `numpy` and run the RTL simulation as a normal function call greatly reduces the amount of effort in adding test cases. Moreover, the `.dump_vcd()` and `.get_resource_estimates()` provide more tools for debugging without having to manually interact with the synthesis tools. We are optimistic that having HCL as a frontend will accelerate the development of AMC. -Both Allo and AMC are ongoing developments that are not ready to be open sourced. However, [the HCL dialect](https://github.com/cornell-zhang/hcl-dialect), [CIRCT](https://github.com/llvm/circt), and [Calyx](https://github.com/cucapra/calyx) all have public GitHub repositories. Finally, we want to thank [Hongzheng](https://www.linkedin.com/in/hongzheng-chen/en) for helping familiarize us with his Allo work. \ No newline at end of file +Both HCL and AMC are ongoing developments that are not ready to be open sourced. However, [the HCL dialect](https://github.com/cornell-zhang/hcl-dialect), [CIRCT](https://github.com/llvm/circt), and [Calyx](https://github.com/cucapra/calyx) all have public GitHub repositories. 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z$HfdP5Z9^-nJGP^Oz=H!T^JzAP{FMgFkvH%K=-27Xdq_-qhC0k=pA)TpKw(bAr2FJBffNd}T zo0R|UzuR5@&(c=^-34>v(O((;|D*N)|Kk740sAO_CO#py-FoidOh4aDDR405>3?|1 z{pv1?>K+cDmiv^dZ6xsD)4KC(9Tru_=J+$ToO#~*H#FZZ1mQN57?VX!jrbnN^%daQ z7J+VceC)-oF>l>GfS!G$C0=$v8tv*bcLlh^i(^Ca|M53_cac}1+3a?lg68p1)XKTS zzE?~H^UPNN%~I%iT~}8Zi4I))vo`fZFZTEpCUqB~|9wIn@Taf!$Fu Date: Tue, 12 Dec 2023 18:26:19 -0500 Subject: [PATCH 24/29] rename project dir --- .../amc_passes.png | Bin .../hcl_dependencies.png | Bin .../index.md | 0 .../overview.svg | 0 4 files changed, 0 insertions(+), 0 deletions(-) rename content/blog/{2023-12-09-allo-amc => 2023-12-09-hcl-amc}/amc_passes.png (100%) rename content/blog/{2023-12-09-allo-amc => 2023-12-09-hcl-amc}/hcl_dependencies.png (100%) rename content/blog/{2023-12-09-allo-amc => 2023-12-09-hcl-amc}/index.md (100%) rename content/blog/{2023-12-09-allo-amc => 2023-12-09-hcl-amc}/overview.svg (100%) diff --git a/content/blog/2023-12-09-allo-amc/amc_passes.png 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From: matth2k Date: Wed, 20 Dec 2023 13:35:22 -0500 Subject: [PATCH 25/29] address first half of comments --- content/blog/2023-12-09-hcl-amc/index.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/content/blog/2023-12-09-hcl-amc/index.md b/content/blog/2023-12-09-hcl-amc/index.md index 75021d90b..9e551bb26 100644 --- a/content/blog/2023-12-09-hcl-amc/index.md +++ b/content/blog/2023-12-09-hcl-amc/index.md @@ -24,13 +24,13 @@ When CPU and GPU optimizations have been exhausted, custom hardware accelerators ### High-Level Synthesis -High-Level Synthesis (HLS) is one such solution to solve the problem of hardware design productivity. The general idea is to raise the level of abstraction from the commonly-used register transfer level (RTL) (e.g. Verilog) to a higher-level language like C/C++. This allows the designer to focus more at the algorithm level and less on the hardware details, such as interfaces and timing. The "magic" of HLS compilers is that it can infer a gate-level mapping from the high-level language to the underlying hardware. The main steps of generating this mapping are scheduling, resource allocation, and binding. In the end, the outputted RTL code from HLS can be synthesized by downstream tools. However, current HLS tools greatly fall short in their promise to free designers from thinking at the architecture level. They rely on special directives (e.g., C++ pragmas) from the designer to guide the optimization process. Oftentimes, the designer must even rewrite their code to fit the HLS compiler's model of computation. +High-Level Synthesis (HLS) is one such solution to solve the problem of hardware design productivity. The general idea is to raise the level of abstraction from the commonly-used register transfer level (RTL) (e.g., Verilog) to a higher-level language like C/C++. This allows the designer to focus more at the algorithm level and less on the hardware details, such as interfaces and timing. The "magic" of HLS compilers is that it can infer a gate-level mapping from the high-level language to the underlying hardware. The main steps of generating this mapping are scheduling, resource allocation, and binding. In the end, the outputted RTL code from HLS can be synthesized by downstream tools. However, current HLS tools greatly fall short in their promise to free designers from thinking at the architecture level. They rely on special directives (e.g., C++ pragmas) from the designer to guide the optimization process. Oftentimes, the designer must even rewrite their code to fit the HLS compiler's model of computation. ### MLIR and Incubator Projects Reinventing HLS with advanced compiler techniques is an active area of research. There are many outstanding HLS tools/frameworks such as [TAPA](https://tapa.readthedocs.io/en/release/overview/overview.html), [Dynamatic](https://dynamatic.epfl.ch/), and [HeteroCL](https://heterocl.csl.cornell.edu/). However, these tools are developed independently with different compilation flows, which brings difficulties of integrating them together. [MLIR](https://mlir.llvm.org/) is a new compiler design paradigm where the source language is compiled through multiple levels of modularized intermediate representations (IRs), also known as dialects. Dialects act like domain-specific languages (DSLs) and can capture the approprate details at each level of abstraction. -The [CIRCT](https://circt.llvm.org/) project expands the MLIR-based development methodology for hardware design. It represents key components of hardware as MLIR dialects such as finite state machines (FSM), pipelines, and interface handshaking. HeteroCL has been migrated to the MLIR ecosystem as a dialect, with a new Python frontend called HCL. HCL decouples the interactions between the algorithm, hardware optimizations, and backend targets to enable productive design and testing. Lastly, Accelerator Memory Compiler (AMC) is an MLIR dialect for representing memory architecture. Its expressiveness is able to capture common memory organization strategies such as partitioning, banking, and arbitration. AMC can be further lowered to Calyx, which is also part of the CIRCT ecosystem. Calyx IR gives us a pathway to finally to synthesizable Verilog. The contribution of this project is that we integrated HCL with AMC to enable a Python frontend for AMC. This allows us to use HCL to describe the algorithm and AMC to describe the memory architecture. The resulting design can be compiled to Verilog and simulated with a single function call. In the end, we hope that this integration will enable a more productive design flow for hardware accelerators as well as help us find more bugs in AMC. +The [CIRCT](https://circt.llvm.org/) project expands the MLIR-based development methodology for hardware design. It represents key components of hardware as MLIR dialects such as finite state machines (FSM), pipelines, and interface handshaking. HeteroCL has been migrated to the MLIR ecosystem as a dialect, with a new Python frontend called HCL. HCL decouples the interactions between the algorithm, hardware optimizations, and backend targets to enable productive design and testing. Lastly, Accelerator Memory Compiler (AMC) is an MLIR dialect for representing memory architecture. Its expressiveness is able to capture common memory organization strategies such as partitioning, banking, and arbitration. AMC can be further lowered to Calyx, which is also integrated with the CIRCT ecosystem. Finally, the Calyx compiler gives us a pathway to synthesizable Verilog. The contribution of this project is that we integrated HCL with AMC to enable a Python frontend for AMC. This allows us to use HCL to describe the algorithm and AMC to describe the memory architecture. The resulting design can be compiled to Verilog and simulated with a single function call. In the end, we hope that this integration will enable a more productive design flow for hardware accelerators as well as help us find more bugs in AMC. ## Design Example @@ -55,7 +55,7 @@ def test_amc(): f = s.build(target="amc") # Run the software simulation by invoking directly np_out = kernel(A, B) - # Now run the hardware simulation with AMC + # Now run the hardware simulation with AMC+Calyx hcl_out = f(A, B) np.testing.assert_array_equal(hcl_out, np_out) ``` @@ -204,7 +204,7 @@ Back to AMC, the custom dialect elaborates the *real* limiting resources of memo } ``` -The role of the AMC compiler is to take in a high-level description of memory organization (as seen above) and figure out how to best compile it to the target architecture. It accounts for some of the properties of underlying architecture, like BRAM size and port count, as well as the context in which the memory is being used. It is a very gradual lowering process, and the explanation of the whole pass pipeline won't even start to fit in this post. However, the following diagram may offer a rough idea of how the core MLIR and AMC dialects to Verilog: +The role of the AMC compiler is to take in a high-level description of memory organization (as seen above) and figure out how to best compile it to the target architecture. It accounts for some of the properties of underlying architecture, like BRAM size and port count, as well as the general context in which the memory is being used. For example, suppose a 2D matrix is being accesssed along its columns. The compiler may bank the memory by the matrix's rows for higher throughput. The memory compilation is a very gradual lowering process, and the explanation of the whole pass pipeline won't even start to fit in this post. However, the following diagram may offer a rough idea of how the core MLIR and AMC dialects to Verilog:

Diagram for AMC pass pipeline From 9461d99a02d5f7b05f913576a906d25065bc9e62 Mon Sep 17 00:00:00 2001 From: matth2k Date: Wed, 20 Dec 2023 14:08:10 -0500 Subject: [PATCH 26/29] address second half of comments --- content/blog/2023-12-09-hcl-amc/index.md | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/content/blog/2023-12-09-hcl-amc/index.md b/content/blog/2023-12-09-hcl-amc/index.md index 9e551bb26..0d6c294e1 100644 --- a/content/blog/2023-12-09-hcl-amc/index.md +++ b/content/blog/2023-12-09-hcl-amc/index.md @@ -34,7 +34,7 @@ The [CIRCT](https://circt.llvm.org/) project expands the MLIR-based development ## Design Example -To use HCL with AMC, the designer only needs to write their kernel in Python. Then, then user can simply specify which Python function to build with the AMC backend. Moreover, AMC acts as a drop-in replacement to the other backends in the HCL ecosystem, making functional testing and debugging seamless. In the far majority of cases, the [NumPy](https://numpy.org/) or the LLVM backend is suitable for use as a golden reference model. In this section, we walk through an example where we functionally verify a kernel built with AMC. Then, we will record some resource estimates and execution times. +To use HCL with AMC, the designer only needs to write their kernel in Python. Then, then user can simply specify which Python function to build with the AMC backend. HCL will do the initial translation of the kernel AST into MLIR, along with some other high-level optimzations. Then, the AMC backend takes it the the rest of the way. Moreover, AMC acts as a drop-in replacement to the other backends in the HCL ecosystem, making functional testing and debugging seamless. In the far majority of cases, the [NumPy](https://numpy.org/) or the LLVM backend is suitable for use as a golden reference model. In this section, we walk through an example where we functionally verify a kernel built with AMC. Then, we will record some resource estimates and execution times. Our illustrative example will be matrix multiplication. What would ordinarily be a cumbersome task when using the vendor tools, like [Vitis HLS](https://www.xilinx.com/products/design-tools/vitis/vitis-hls.html), becomes a simple, 5 minute exercise. First, we specify some inputs initialized to random values. Then, `build()` the accelerator. Finally, we call both the software and hardware simulations and check their outputs. Compared to a C/C++ based tool flow, the amount of boilerplate code and scripting is reduced to near zero. In the end, we can represent this application with only 18 lines of code: @@ -50,8 +50,10 @@ def test_amc(): def kernel(A: int32[N, N], B: int32[N, N]) -> int32[N, N]: return matmul(A, B) - # Build the accelerator with AMC backend + # Traverse the kernel AST + # and create handle to Allo customizations s = customize(kernel) + # Build the accelerator with AMC backend f = s.build(target="amc") # Run the software simulation by invoking directly np_out = kernel(A, B) @@ -204,7 +206,9 @@ Back to AMC, the custom dialect elaborates the *real* limiting resources of memo } ``` -The role of the AMC compiler is to take in a high-level description of memory organization (as seen above) and figure out how to best compile it to the target architecture. It accounts for some of the properties of underlying architecture, like BRAM size and port count, as well as the general context in which the memory is being used. For example, suppose a 2D matrix is being accesssed along its columns. The compiler may bank the memory by the matrix's rows for higher throughput. The memory compilation is a very gradual lowering process, and the explanation of the whole pass pipeline won't even start to fit in this post. However, the following diagram may offer a rough idea of how the core MLIR and AMC dialects to Verilog: +In the above snippet, AMC IR is being used to declare a simple memory interface. The body is the implementation of said memory. First, the definition starts with an `amc.alloc` operation which represents the memory banks themselves. Then, `amc.create_port` is used to create handles to ports on those banks. Finally, `amc.extern` exposes those ports in the memory interface. In this case, the port types are dynamic, meaing that they have non-static latency for every read/write request. This memory module is a very simple example. Given a more elaborate application, you can find very interesting interactions from the compositions of AMC operations not shown here (`amc.merge`, `amc.reshape`, `amc.arbiter`, ...). + +The role of the AMC compiler is to take in a high-level description of memory organization (as seen above) and figure out how to best compile it to the target architecture. It accounts for some of the properties of underlying architecture, like BRAM size and port count. Moreover, AMC attempts to exploit the context in which the memory is being used for optimization. For example, suppose a 2D matrix is being accesssed along its columns. The compiler may bank the memory by the matrix's rows for higher throughput. Overall, the memory compilation is a very gradual lowering process, and the explanation of the whole pass pipeline won't fit in this post about the frontend. However, the following diagram may offer a rough idea of how the core MLIR and AMC dialects to Verilog:
Diagram for AMC pass pipeline From 095d8c186180c8f3140d3561d9d0d97bc54dc0b2 Mon Sep 17 00:00:00 2001 From: matth2k Date: Wed, 20 Dec 2023 14:10:05 -0500 Subject: [PATCH 27/29] typo --- content/blog/2023-12-09-hcl-amc/index.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/content/blog/2023-12-09-hcl-amc/index.md b/content/blog/2023-12-09-hcl-amc/index.md index 0d6c294e1..8a8e9ba3c 100644 --- a/content/blog/2023-12-09-hcl-amc/index.md +++ b/content/blog/2023-12-09-hcl-amc/index.md @@ -208,7 +208,7 @@ Back to AMC, the custom dialect elaborates the *real* limiting resources of memo In the above snippet, AMC IR is being used to declare a simple memory interface. The body is the implementation of said memory. First, the definition starts with an `amc.alloc` operation which represents the memory banks themselves. Then, `amc.create_port` is used to create handles to ports on those banks. Finally, `amc.extern` exposes those ports in the memory interface. In this case, the port types are dynamic, meaing that they have non-static latency for every read/write request. This memory module is a very simple example. Given a more elaborate application, you can find very interesting interactions from the compositions of AMC operations not shown here (`amc.merge`, `amc.reshape`, `amc.arbiter`, ...). -The role of the AMC compiler is to take in a high-level description of memory organization (as seen above) and figure out how to best compile it to the target architecture. It accounts for some of the properties of underlying architecture, like BRAM size and port count. Moreover, AMC attempts to exploit the context in which the memory is being used for optimization. For example, suppose a 2D matrix is being accesssed along its columns. The compiler may bank the memory by the matrix's rows for higher throughput. Overall, the memory compilation is a very gradual lowering process, and the explanation of the whole pass pipeline won't fit in this post about the frontend. However, the following diagram may offer a rough idea of how the core MLIR and AMC dialects to Verilog: +The role of the AMC compiler is to take in a high-level description of memory organization (as seen above) and figure out how to best compile it to the target architecture. It accounts for some of the properties of underlying architecture, like BRAM size and port count. Moreover, AMC attempts to exploit the context in which the memory is being used for optimization. For example, suppose a 2D matrix is being accesssed along its columns. The compiler may bank the memory by the matrix's rows for higher throughput. Overall, the memory compilation is a very gradual lowering process, and the explanation of the whole pass pipeline won't fit in this post about the frontend. However, the following diagram may offer a rough idea of how the core MLIR and AMC dialects lower to Verilog:
Diagram for AMC pass pipeline From 0feb478e5c6dd84306cf19bad2a2d048cf68c679 Mon Sep 17 00:00:00 2001 From: matth2k Date: Wed, 20 Dec 2023 14:10:46 -0500 Subject: [PATCH 28/29] typo --- content/blog/2023-12-09-hcl-amc/index.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/content/blog/2023-12-09-hcl-amc/index.md b/content/blog/2023-12-09-hcl-amc/index.md index 8a8e9ba3c..a602d3e61 100644 --- a/content/blog/2023-12-09-hcl-amc/index.md +++ b/content/blog/2023-12-09-hcl-amc/index.md @@ -206,7 +206,7 @@ Back to AMC, the custom dialect elaborates the *real* limiting resources of memo } ``` -In the above snippet, AMC IR is being used to declare a simple memory interface. The body is the implementation of said memory. First, the definition starts with an `amc.alloc` operation which represents the memory banks themselves. Then, `amc.create_port` is used to create handles to ports on those banks. Finally, `amc.extern` exposes those ports in the memory interface. In this case, the port types are dynamic, meaing that they have non-static latency for every read/write request. This memory module is a very simple example. Given a more elaborate application, you can find very interesting interactions from the compositions of AMC operations not shown here (`amc.merge`, `amc.reshape`, `amc.arbiter`, ...). +In the above snippet, AMC IR is being used to declare a simple memory interface. The body is the implementation of said memory. First, the definition starts with an `amc.alloc` operation which represents the memory banks themselves. Then, `amc.create_port` is used to create handles to ports on those banks. Finally, `amc.extern` exposes those ports in the memory interface. In this case, the port types are dynamic, meaning that they have non-static latency for every read/write request. This memory module is a very simple example. Given a more elaborate application, you can find very interesting interactions from the compositions of AMC operations not shown here (`amc.merge`, `amc.reshape`, `amc.arbiter`, ...). The role of the AMC compiler is to take in a high-level description of memory organization (as seen above) and figure out how to best compile it to the target architecture. It accounts for some of the properties of underlying architecture, like BRAM size and port count. Moreover, AMC attempts to exploit the context in which the memory is being used for optimization. For example, suppose a 2D matrix is being accesssed along its columns. The compiler may bank the memory by the matrix's rows for higher throughput. Overall, the memory compilation is a very gradual lowering process, and the explanation of the whole pass pipeline won't fit in this post about the frontend. However, the following diagram may offer a rough idea of how the core MLIR and AMC dialects lower to Verilog: From 7bc1ebe0480700f6c25f983330176d7fa6e8da63 Mon Sep 17 00:00:00 2001 From: matth2k Date: Wed, 20 Dec 2023 14:11:59 -0500 Subject: [PATCH 29/29] rephrase last sentence on AMC IR --- content/blog/2023-12-09-hcl-amc/index.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/content/blog/2023-12-09-hcl-amc/index.md b/content/blog/2023-12-09-hcl-amc/index.md index a602d3e61..b088cc5b5 100644 --- a/content/blog/2023-12-09-hcl-amc/index.md +++ b/content/blog/2023-12-09-hcl-amc/index.md @@ -206,7 +206,7 @@ Back to AMC, the custom dialect elaborates the *real* limiting resources of memo } ``` -In the above snippet, AMC IR is being used to declare a simple memory interface. The body is the implementation of said memory. First, the definition starts with an `amc.alloc` operation which represents the memory banks themselves. Then, `amc.create_port` is used to create handles to ports on those banks. Finally, `amc.extern` exposes those ports in the memory interface. In this case, the port types are dynamic, meaning that they have non-static latency for every read/write request. This memory module is a very simple example. Given a more elaborate application, you can find very interesting interactions from the compositions of AMC operations not shown here (`amc.merge`, `amc.reshape`, `amc.arbiter`, ...). +In the above snippet, AMC IR is being used to declare a simple memory interface. The body is the implementation of said memory. First, the definition starts with an `amc.alloc` operation which represents the memory banks themselves. Then, `amc.create_port` is used to create handles to ports on those banks. Finally, `amc.extern` exposes those ports in the memory interface. In this case, the port types are dynamic, meaning that they have non-static latency for every read/write request. While this memory module is a very simple example, you can encounter very interesting interactions from the compositions of AMC operations, especially the ones not shown here (`amc.merge`, `amc.reshape`, `amc.arbiter`, ...). The role of the AMC compiler is to take in a high-level description of memory organization (as seen above) and figure out how to best compile it to the target architecture. It accounts for some of the properties of underlying architecture, like BRAM size and port count. Moreover, AMC attempts to exploit the context in which the memory is being used for optimization. For example, suppose a 2D matrix is being accesssed along its columns. The compiler may bank the memory by the matrix's rows for higher throughput. Overall, the memory compilation is a very gradual lowering process, and the explanation of the whole pass pipeline won't fit in this post about the frontend. However, the following diagram may offer a rough idea of how the core MLIR and AMC dialects lower to Verilog: