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Breathe (more) life into our release cycle #250
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Awwww. 😍 pets ego I think this is a great idea, the simplest way to start would be to actually run the unit tests on the device for every release and attach the output to the release in some form. Q2 release is in ~7w, we should agree on a timeline, otherwise this may lead to some serious yak shaving.
Contractually not allowed to speak ill of The World's #1™ embedded test shield… 😅 Might be interesting to create just one PCB that fits on all the Discovery and Nucleo-32/64/144 boards. That would be some serious footprint-overlay-magic*, but would save on costs. I've been thinking about hardware test tools and setups a lot and have many ideas bouncing around my head, so I'll sketch them down. I'm going to be fairly busy until end of May, so this could take a while. * do not attempt, professional engineer in a closed room |
Thanks for the feedback. I'm not yet aiming at an own board. That's something for later.
That's a great idea. We haven't done that for years. For AVRs this is only possible for the ATmega2560 and I don't think I have access to one at the moment. If my preferred seller from Asia is quick enough a board may arrive before end of Q2. Is there a strategy to split the unittest into smaller chunks which can be tested individually? That's a great first step to first introduce a simple workflow. I would call it an achievement if we manually run unittests on an ATmega, a STM32L4 and a STM32F4 for the next 2017q2 release. Agreed on that? Maybe I prepare a breadboard with
Uart is tested by using the logger to observe the example.
For the pinout issue: The simplest approach would be:
The FPGA can be reconfigured to adopt different pinouts to our sensors board. |
Paging @dergraaf, paging @dergraaf. We need a knowledge infusion stat!
👍 Let's do it.
I think we should start with a wooden board and a 5V power supply and put like 10 different dev boards on it, then figure out how we are going to program and evaluate them. I'm currently trying to get the ESP8266 port of BMP to work, then we'd have wireless BMPs for cheap and could connect them to Ze Klaot™. No platform-dependent USB mess (cc @ekiwi), only one 5V power rail. Don't get me wrong, I absolutely agree on the FPGA as a vision, but I think the next logical step would be to deploy the unit tests as part of CI. That actually involves a lot of non-embedded work as well. |
Well, the typical way would be to group the test into test suites which then can be combined or run individually. Unfortunately this has not been implemented in the xpcc unittest tools yet.
I like that idea 😄 |
I'd like first to convert the runner templates to Jinja2 templates, so that the iterations are done with Jinja ('cause of yak shaving). The unittest creates a blob which is poured in here. But I have not yet found out how (technically) to integrate the Jinja2Template Builder in the unittest.py. Any suggestions? |
I ran a unittest on STM32L4 Nucleo board (after disabling one test).
I will look into the bmp085 issues. I changed the resumable_test:904 - TEST_ASSERT_TRUE(sizeof(result) == 1);
+ TEST_ASSERT_EQUALS(sizeof(result), 1U); so that the unittest spits out whats expected and what is the actual result. |
Ah. The assumption I made for - TEST_ASSERT_TRUE(sizeof(result) == 1);
+ TEST_ASSERT_EQUALS(sizeof(result), sizeof(uint_fast8_t)); |
Finally that's the result on an Nucleo L476RG board
Actually it runs for some seconds! Steps to reproduce:
Change the target to
|
Yes, please. It makes more sense to proved a board here, than a device, since the xpcc logger and programmer is already defined that way. This should enable unittest execution on all boards then. |
Automatically running unittest on ST Nucleo L476RG using Docker
Docker containers are here. |
Very nice, just in time for the 2017q2 release this weekend! |
Thanks, great to hear that. Finishing something for the 2017q2 release was my goal ... after some time of inactivity. BTW, I won't be able to fix the I2C for 2017q2 release. But definitely after that. |
After introducing a new release cycle (#160, #237), the next release is knocking on the door (2017q2 tags at #249 and #248 ;-) I really appreciate the professional management of @salkinium!
What about adding a (manual) release test with some dev boards to that release cycle?
HWUT is dead, so lets start first with something easier.
Dev boards with general availability are IMHO
They could be wired together with some LEDs, TTL2USB, CAN transceivers, well known sensors (I2C, SPI, ...). There should be a generally accepted test setup, e.g. like the mbed CI Test Shield.
The QA team 🥇 should not spend more than 15 minutes to run some examples to verify that at least in that setup something works. The test coverage may still be small but may catch some nasty errors that may be introduced by e.g. updating header files.
I would like to discuss some options for advancing the release cycle.
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