Latency Consistency in Sequential and Interleaved Memory Writes

[ashuthosh-mr]

I was running a few basic tests with the Mempool. During these tests, I tried to measure the time taken to write to sequential memory and interleaved memory.

Issue:

In the attached code, I write 50 times using core 5 to 50 different consecutive locations. The latency I get is 173 cycles irrespective of which memory region I use.

Configuration:

Mempool: 256 cores
Stack Space: 1024 bytes per core
Sequential Memory per Core: 2048 bytes per core

Expected Behavior:

My expectation is that if I write to sequential space within the tile from the core belonging to the same tile, it should take 50 cycles for 50 writes. And if I write to locations in the other tile, depending on the hierarchy, the latency should vary.

Request:

Could you please let me know if I am doing it right? Any insights or guidance would be appreciated.
main.c.txt