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The current memory island does not support atomic operations or LR/SC, but this would be useful for many SoC designs. Special consideration will need to be taken to ensure consistency across all ports. Arguably, this will only need to be supported on narrow channels, as the idea for wide channels is mostly for massive data transfer, but this is debatable. Furthermore, reservations will need to be invalidated by all writes, regardless of narrow or wide.
Some inspiration can be taken from OBI and the safety island converters.
The text was updated successfully, but these errors were encountered:
The current memory island does not support atomic operations or LR/SC, but this would be useful for many SoC designs. Special consideration will need to be taken to ensure consistency across all ports. Arguably, this will only need to be supported on narrow channels, as the idea for wide channels is mostly for massive data transfer, but this is debatable. Furthermore, reservations will need to be invalidated by all writes, regardless of narrow or wide.
Some inspiration can be taken from OBI and the safety island converters.
The text was updated successfully, but these errors were encountered: