Configure the bus guard for vivado simulation

[NikoSalamini]

I am currently setting up a Vivado design using AXI4 VIPs to test the AXI-RT unit. However, I've encountered several issues during the configuration process. Specifically, when I added the AXI-RT unit to the block design and ran a simulation, I received errors due to missing headers. It seems that the packaged IP's source code refers to directories or files that are not included in the project. Below is a list of the missing headers:

`include "axi/assign.svh" 
`include "axi/typedef.svh" 
`include "uvm_macros.svh" 
`include "common_cells/registers.svh" 
`include "common_cells/assertions.svh" 
`include "register_interface/typedef.svh" 
`include "register_interface/assign.svh" 
`include "axi-rt/assign.svh" 
`include "axi-rt/port.svh" 

I resolved the previous issue by adding the missing headers from older commits to the packaged IP source design folder. However, I've encountered another problem: the variable used to check whether the Vivado simulator is running is incorrect. It was originally specified as XSIM, but it should be XILINX_SIMULATOR. This misconfiguration leads to an error related to the unsupported iff feature during simulation. Here's an example:

`ifndef VERILATOR
`ifndef XSIM --> XILINX_SIMULATOR
  initial begin
    assume (NumPending > 0) else $fatal(1, "At least one pending transaction required.");
  end
  default disable iff (!rst_ni);
  aw_overflow: assert property (@(posedge clk_i)
      (pending_aw_q == '1) |=> (pending_aw_q != '0)) else
      $fatal(1, "pending_aw_q overflowed");
  ar_overflow: assert property (@(posedge clk_i)
      (pending_ar_q == '1) |=> (pending_ar_q != '0)) else
      $fatal(1, "pending_ar_q overflowed");
  aw_underflow: assert property (@(posedge clk_i)
      (pending_aw_q == '0) |=> (pending_aw_q != '1)) else
      $fatal(1, "pending_aw_q underflowed");
  ar_underflow: assert property (@(posedge clk_i)
      (pending_ar_q == '0) |=> (pending_ar_q != '1)) else
      $fatal(1, "pending_ar_q underflowed");
`endif
`endif

Now the simulation runs. However, I can't find a way to claim access to the bus guard correctly. This is my design:

This is the code I am using to configure the axi_rt IP:

initial begin
    //Create agents
    slv_agent = new("slave vip agent",DUT.design_1_i.axi_vip_1.inst.IF);
    master_agent_full = new("master vip full axi4 agent",DUT.design_1_i.axi_vip_2.inst.IF);
    master_agent_config = new("master vip axi4 lite agent" ,DUT.design_1_i.axi_vip_0.inst.IF);
 
    // set tag for agents for easy debug
    slv_agent.set_agent_tag("Slave VIP");
    master_agent_full.set_agent_tag("Master VIP full AXI4");
    master_agent_config.set_agent_tag("Master VIP AXI4 lite");
 
    // set print out verbosity level.
    master_agent_full.set_verbosity(400);
    master_agent_config.set_verbosity(400);
 
    //Start the agent
    slv_agent.start_slave();
    master_agent_full.start_master();
    master_agent_config.start_master();

    // reset
    aresetn = 0; 
    #250ns  
    aresetn = 1;
    #50ns
    
    /* configure the IP */

    prot = 0;  // Assuming normal, non-secure, data access for protection

    // claim access
    master_agent_config.AXI4LITE_WRITE_BURST(32'h000007ff, prot, 32'h00000007, resp); // WHICH ADDRESS SHOULD I PUT HERE 

    // read id register
    master_agent_config.AXI4LITE_READ_BURST(32'h000007ff, prot, read_data, resp);

    // set region
    start_addr = 32'h00000000;
    end_addr = 32'h00000000;
    region_id = 0;
    mgr_id = 0;

    start_addr_low  = start_addr[31:0];
    start_addr_high = start_addr[63:32];
    end_addr_low    = end_addr[31:0];
    end_addr_high   = end_addr[63:32];

    // Write the end address high
    addr = AXI_RT_END_ADDR_SUB_HIGH_0_OFFSET + AXI_RT_PARAM_NUM_SUB * mgr_id * 4 + region_id * 4;
    master_agent_config.AXI4LITE_WRITE_BURST(addr, prot, end_addr_high, resp);
    master_agent_config.AXI4LITE_READ_BURST(addr, prot, read_data, resp);
    if (read_data !== end_addr_high) begin
        $error("End address high readback mismatch: Expected %h, got %h", end_addr_high, read_data);
    end

    // Write the end address low
    addr = AXI_RT_END_ADDR_SUB_LOW_0_OFFSET + AXI_RT_PARAM_NUM_SUB * mgr_id * 4 + region_id * 4;
    master_agent_config.AXI4LITE_WRITE_BURST(addr, prot, end_addr_low, resp);
    master_agent_config.AXI4LITE_READ_BURST(addr, prot, read_data, resp);
    if (read_data !== end_addr_low) begin
        $error("End address low readback mismatch: Expected %h, got %h", end_addr_low, read_data);
    end

    // Write the start address low
    addr = AXI_RT_START_ADDR_SUB_LOW_0_OFFSET + AXI_RT_PARAM_NUM_SUB * mgr_id * 4 + region_id * 4;
    master_agent_config.AXI4LITE_WRITE_BURST(addr, prot, start_addr_low, resp);
    master_agent_config.AXI4LITE_READ_BURST(addr, prot, read_data, resp);
    if (read_data !== start_addr_low) begin
        $error("Start address low readback mismatch: Expected %h, got %h", start_addr_low, read_data);
    end

    // Write the start address high
    addr = AXI_RT_START_ADDR_SUB_HIGH_0_OFFSET + AXI_RT_PARAM_NUM_SUB * mgr_id * 4 + region_id * 4;
    master_agent_config.AXI4LITE_WRITE_BURST(addr, prot, start_addr_high, resp);
    master_agent_config.AXI4LITE_READ_BURST(addr, prot, read_data, resp);
    if (read_data !== start_addr_high) begin
        $error("Start address high readback mismatch: Expected %h, got %h", start_addr_high, read_data);
    end
    
    // continue config...
    

Since I have no bus but a direct connection to the config interface, which address should I put to refer to the special register for claiming access to the register address space of the axi rt unit?