Adding a new processor model and more detailed build instructions

[TheCopperMind]

Hi,
I'm a master student and I'm starting my thesis on RISC-V multithreading extensions, and I think Ripes would be awesome to work with as part of that!

I think it would be great to have a guide on how to add new processor models or how to change the existing ones. I also believe a more detailed guide on the build process would be convenient, as I've tried to build the project for a while to no avail.

[mortbopet]

Hi @TheCopperMind !
First of all, thank you for considering working with Ripes on a source-code level.

Indeed the currently provided build instructions are very sparse, and i'll take a look at how i can improve that. In the meantime, i'd say your best bet is to

1. Download Qt and get any of their example projects up and running
2. Then follow the instructions on the front page

Using Qt's own IDE QtCreator can also simplify the process, since it already has registration of the various Qt components built-in. In any case, feel free to shoot me an e-mail or raise an issue if things get stuck.

Next, on adding processor models. That is also a TODO in the wiki, which i should probably get done some day! At the moment, the lackluster answer is that the best way to add processor models is to look at the existing ones and copy the structure of how they've been included into the program. For changing them, your best bet is to read through one of the implementations to get a feel for the VSRTL API. Hopefully it should be familiar if you've done a bit of work with HDLs before.

Lastly, I've also been toying with the idea of using Verilator generated processors as a backend for Ripes. With the current mechanism (using VSRTL), we get the added benefit of a visualization. However, VSRTL is not a fully-fledged HDL and users may find it difficult to express some constucts in it. For an example, see this branch, where the PicoRV32 processor is integrated into the Ripes environment.

[TheCopperMind]

Great! I'll make sure to try this out!

[TheCopperMind]

@mortbopet What is the workflow for using Verilator as a backend?

[mortbopet]

Since there might be a bit of interest in this, i'll go ahead and write a wiki entry!

[mortbopet]

This should hopefully explain the processor: https://github.com/mortbopet/Ripes/wiki/Adding-new-processor-models#experimental-verilator-processor-models-in-ripes
Let me know if something is unclear/doesn't work!