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sregs.h
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sregs.h
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const sysreg sysregs[] = {
{3, 0, 1, 0, 1, "ACTLR_EL1"},
{3, 4, 1, 0, 1, "ACTLR_EL2"},
{3, 6, 1, 0, 1, "ACTLR_EL3"},
{3, 1, 0, 0, 7, "AIDR_EL1"},
{3, 0, 5, 1, 0, "AFSR0_EL1"},
{3, 4, 5, 1, 0, "AFSR0_EL2"},
{3, 6, 5, 1, 0, "AFSR0_EL3"},
{3, 0, 5, 1, 1, "AFSR1_EL1"},
{3, 4, 5, 1, 1, "AFSR1_EL2"},
{3, 6, 5, 1, 1, "AFSR1_EL3"},
{3, 0, 10, 3, 0, "AMAIR_EL1"},
{3, 4, 10, 3, 0, "AMAIR_EL2"},
{3, 6, 10, 3, 0, "AMAIR_EL3"},
{3, 1, 0, 0, 0, "CCSIDR_EL1"},
{3, 1, 0, 0, 1, "CLIDR_EL1"},
{3, 0, 1, 0, 2, "CPACR_EL1"},
{3, 4, 1, 1, 2, "CPTR_EL2"},
{3, 6, 1, 1, 2, "CPTR_EL3"},
{3, 2, 0, 0, 0, "CSSELR_EL1"},
{3, 3, 0, 0, 1, "CTR_EL0"},
{3, 0, 12, 1, 1, "DISR_EL1"},
{3, 0, 5, 3, 0, "ERRIDR_EL1"},
{3, 0, 5, 3, 1, "ERRSELR_EL1"},
{3, 0, 5, 4, 3, "ERXADDR_EL1"},
{3, 0, 5, 4, 1, "ERXCTLR_EL1"},
{3, 0, 5, 4, 0, "ERXFR_EL1"},
{3, 0, 5, 5, 0, "ERXMISC0_EL1"},
{3, 0, 5, 5, 1, "ERXMISC1_EL1"},
{3, 0, 5, 4, 2, "ERXSTATUS_EL1"},
{3, 0, 5, 2, 0, "ESR_EL1"},
{3, 4, 5, 2, 0, "ESR_EL2"},
{3, 6, 5, 2, 0, "ESR_EL3"},
{3, 4, 1, 1, 7, "HACR_EL2"},
{3, 4, 1, 1, 0, "HCR_EL2"},
{3, 0, 0, 1, 3, "ID_AFR0_EL1"},
{3, 0, 0, 1, 2, "ID_DFR0_EL1"},
{3, 0, 0, 2, 0, "ID_ISAR0_EL1"},
{3, 0, 0, 2, 1, "ID_ISAR1_EL1"},
{3, 0, 0, 2, 2, "ID_ISAR2_EL1"},
{3, 0, 0, 2, 3, "ID_ISAR3_EL1"},
{3, 0, 0, 2, 4, "ID_ISAR4_EL1"},
{3, 0, 0, 2, 5, "ID_ISAR5_EL1"},
{3, 0, 0, 2, 7, "ID_ISAR6_EL1"},
{3, 0, 0, 1, 4, "ID_MMFR0_EL1"},
{3, 0, 0, 1, 5, "ID_MMFR1_EL1"},
{3, 0, 0, 1, 6, "ID_MMFR2_EL1"},
{3, 0, 0, 1, 7, "ID_MMFR3_EL1"},
{3, 0, 0, 2, 6, "ID_MMFR4_EL1"},
{3, 0, 0, 1, 0, "ID_PFR0_EL1"},
{3, 0, 0, 1, 1, "ID_PFR1_EL1"},
{3, 0, 0, 5, 0, "ID_AA64DFR0_EL1"},
{3, 0, 0, 6, 0, "ID_AA64ISAR0_EL1"},
{3, 0, 0, 6, 1, "ID_AA64ISAR1_EL1"},
{3, 0, 0, 7, 0, "ID_AA64MMFR0_EL1"},
{3, 0, 0, 7, 1, "ID_AA64MMFR1_EL1"},
{3, 0, 0, 7, 2, "ID_AA64MMFR2_EL1"},
{3, 0, 0, 4, 0, "ID_AA64PFR0_EL1"},
{3, 4, 5, 0, 1, "IFSR32_EL2"},
{3, 0, 10, 4, 3, "LORC_EL1"},
{3, 0, 10, 4, 7, "LORID_EL1"},
{3, 0, 10, 4, 2, "LORN_EL1"},
{3, 6, 1, 3, 1, "MDCR_EL3"},
{3, 0, 0, 0, 0, "MIDR_EL1"},
{3, 0, 0, 0, 5, "MPIDR_EL1"},
{3, 0, 7, 4, 0, "PAR_EL1"},
{3, 6, 12, 0, 1, "RVBAR_EL3"},
{3, 0, 0, 0, 6, "REVIDR_EL1"},
{3, 0, 1, 0, 0, "SCTLR_EL1"},
{3, 6, 1, 0, 0, "SCTLR_EL3"},
{3, 0, 2, 0, 2, "TCR_EL1"},
{3, 4, 2, 0, 2, "TCR_EL2"},
{3, 6, 2, 0, 2, "TCR_EL3"},
{3, 0, 2, 0, 0, "TTBR0_EL1"},
{3, 4, 2, 0, 0, "TTBR0_EL2"},
{3, 6, 2, 0, 0, "TTBR0_EL3"},
{3, 0, 2, 0, 1, "TTBR1_EL1"},
{3, 4, 2, 0, 1, "TTBR1_EL2"},
{3, 4, 12, 1, 1, "VDISR_EL2"},
{3, 4, 5, 2, 3, "VSESR_EL2"},
{3, 4, 2, 1, 2, "VTCR_EL2"},
{3, 4, 2, 1, 0, "VTTBR_EL2"},
{3, 5, 5, 1, 0, "AFSR0_EL12"},
{3, 5, 5, 1, 1, "AFSR1_EL12"},
{3, 5, 10, 3, 0, "AMAIR_EL12"},
{3, 3, 14, 0, 0, "CNTFRQ_EL0"},
{3, 4, 14, 1, 0, "CNTHCTL_EL2"},
{3, 4, 14, 2, 1, "CNTHP_CTL_EL2"},
{3, 4, 14, 2, 2, "CNTHP_CVAL_EL2"},
{3, 4, 14, 2, 0, "CNTHP_TVAL_EL2"},
{3, 4, 14, 3, 1, "CNTHV_CTL_EL2"},
{3, 4, 14, 3, 2, "CNTHV_CVAL_EL2"},
{3, 4, 14, 3, 0, "CNTHV_TVAL_EL2"},
{3, 0, 14, 1, 0, "CNTKCTL_EL1"},
{3, 5, 14, 1, 0, "CNTKCTL_EL12"},
{3, 3, 14, 2, 1, "CNTP_CTL_EL0"},
{3, 5, 14, 2, 1, "CNTP_CTL_EL02"},
{3, 3, 14, 2, 2, "CNTP_CVAL_EL0"},
{3, 5, 14, 2, 2, "CNTP_CVAL_EL02"},
{3, 3, 14, 2, 0, "CNTP_TVAL_EL0"},
{3, 5, 14, 2, 0, "CNTP_TVAL_EL02"},
{3, 3, 14, 0, 1, "CNTPCT_EL0"},
{3, 7, 14, 2, 1, "CNTPS_CTL_EL1"},
{3, 7, 14, 2, 2, "CNTPS_CVAL_EL1"},
{3, 7, 14, 2, 0, "CNTPS_TVAL_EL1"},
{3, 3, 14, 3, 1, "CNTV_CTL_EL0"},
{3, 5, 14, 3, 1, "CNTV_CTL_EL02"},
{3, 3, 14, 3, 2, "CNTV_CVAL_EL0"},
{3, 5, 14, 3, 2, "CNTV_CVAL_EL02"},
{3, 3, 14, 3, 0, "CNTV_TVAL_EL0"},
{3, 5, 14, 3, 0, "CNTV_TVAL_EL02"},
{3, 3, 14, 0, 2, "CNTVCT_EL0"},
{3, 4, 14, 0, 3, "CNTVOFF_EL2"},
{3, 0, 13, 0, 1, "CONTEXTIDR_EL1"},
{3, 5, 13, 0, 1, "CONTEXTIDR_EL12"},
{3, 4, 13, 0, 1, "CONTEXTIDR_EL2"},
{3, 5, 1, 0, 2, "CPACR_EL12"},
{3, 6, 1, 1, 2, "CPTR_EL3"},
{3, 4, 3, 0, 0, "DACR32_EL2"},
{3, 5, 5, 2, 0, "ESR_EL12"},
{3, 0, 6, 0, 0, "FAR_EL1"},
{3, 5, 6, 0, 0, "FAR_EL12"},
{3, 4, 6, 0, 0, "FAR_EL2"},
{3, 6, 6, 0, 0, "FAR_EL3"},
{3, 4, 5, 3, 0, "FPEXC32_EL2"},
{3, 4, 6, 0, 4, "HPFAR_EL2"},
{3, 4, 1, 1, 3, "HSTR_EL2"},
{3, 0, 0, 5, 4, "ID_AA64AFR0_EL1"},
{3, 0, 0, 5, 5, "ID_AA64AFR1_EL1"},
{3, 0, 0, 5, 1, "ID_AA64DFR1_EL1"},
{3, 0, 0, 4, 1, "ID_AA64PFR1_EL1"},
{3, 0, 12, 1, 0, "ISR_EL1"},
{3, 0, 10, 4, 1, "LOREA_EL1"},
{3, 0, 10, 4, 0, "LORSA_EL1"},
{3, 0, 10, 2, 0, "MAIR_EL1"},
{3, 5, 10, 2, 0, "MAIR_EL12"},
{3, 4, 10, 2, 0, "MAIR_EL2"},
{3, 6, 10, 2, 0, "MAIR_EL3"},
{3, 4, 1, 1, 1, "MDCR_EL2"},
{3, 0, 0, 3, 0, "MVFR0_EL1"},
{3, 0, 0, 3, 1, "MVFR1_EL1"},
{3, 0, 0, 3, 2, "MVFR2_EL1"},
{3, 6, 12, 0, 2, "RMR_EL3"},
{3, 6, 1, 1, 0, "SCR_EL3"},
{3, 5, 1, 0, 0, "SCTLR_EL12"},
{3, 4, 1, 0, 0, "SCTLR_EL2"},
{3, 6, 1, 1, 1, "SDER32_EL3"},
{3, 5, 2, 0, 2, "TCR_EL12"},
{3, 3, 13, 0, 2, "TPIDR_EL0"},
{3, 0, 13, 0, 4, "TPIDR_EL1"},
{3, 4, 13, 0, 2, "TPIDR_EL2"},
{3, 6, 13, 0, 2, "TPIDR_EL3"},
{3, 3, 13, 0, 3, "TPIDRRO_EL0"},
{3, 5, 2, 0, 0, "TTBR0_EL12"},
{3, 5, 2, 0, 1, "TTBR1_EL12"},
{3, 0, 12, 0, 0, "VBAR_EL1"},
{3, 5, 12, 0, 0, "VBAR_EL12"},
{3, 4, 12, 0, 0, "VBAR_EL2"},
{3, 6, 12, 0, 0, "VBAR_EL3"},
{3, 4, 0, 0, 5, "VMPIDR_EL2"},
{3, 4, 0, 0, 0, "VPIDR_EL2"},
};