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edge_port.c
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edge_port.c
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// SPDX-License-Identifier: GPL-2.0
/* TTTech EDGE/DE-IP Linux driver
* Copyright(c) 2018 TTTech Computertechnik AG.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, see <http://www.gnu.org/licenses/>.
*
* The full GNU General Public License is included in this distribution in
* the file called "COPYING".
*
* Contact Information:
* TTTech Computertechnik AG, Schoenbrunnerstrasse 7, 1040 Vienna, Austria
*/
#include <linux/version.h>
#include <linux/etherdevice.h>
#include <linux/if_bridge.h>
#include <linux/netdevice.h>
#include "edge_ac.h"
#include "edge_com.h"
#include "edge_br_vlan.h"
#include "edge_br_fdb.h"
#include "edge_bridge.h"
#include "edge_link.h"
#include "edge_port.h"
#include "edge_preempt.h"
#include "edge_sched.h"
#include "edge_stat.h"
#include "edge_time.h"
#include "edge_util.h"
#include "edge_fqtss.h"
#include "edge_br_sid.h"
#include "edge_frer.h"
struct edgx_ptfillqu {
/* Protect the control register for buffer fill level capture */
spinlock_t lock;
};
struct edgx_pt {
struct edgx_br *parent;
struct net_device *netdev;
struct edgx_com_hdl *hcom;
struct edgx_link *link;
ptid_t ptid;
/* From here it's specific to bridge ports */
edgx_io_t *iobase;
struct edgx_time *time;
struct edgx_stat_hdl *hstat;
struct edgx_ptfillqu fillqu;
struct edgx_sched *sched;
struct edgx_preempt *preempt;
struct edgx_fqtss *fqtss;
struct mutex reg_lock; /* Protects register access */
};
#define _PT_STP_FWD 0x0
#define _PT_STP_LEARN 0x1
#define _PT_STP_DISABLED 0x2
#define _MAX_PRIO_VAL (EDGX_BR_NUM_PCP - 1)
#define _TX8_DEF_VAL 0x76543210
#define _TX4_DEF_VAL 0x33221100
#define _PRIO_REGEN_LO 0x16
#define _PRIO_REGEN_HI 0x18
#define _QUEUE_TBL_LO 0x20
#define _QUEUE_TBL_HI 0x22
#define _TYPE_PRIO_REGEN 0xab
#define _TYPE_QUEUE_TBL 0xcd
#define EDGX_PT_WDT_MS 2000U
#define _BRPT_FLAGS (BR_LEARNING | BR_LEARNING_SYNC | BR_FLOOD)
/* VID 4095 (0xFFF) is reserved for implementation use.
* We don't need any further guard in, as Linux bridge code does not allow the
* creation of this VLAN.
*/
#define _PVID_NONE 0xFFF
#define _STAT_PORT_BASE 0x200
#define _FL_CAPT 0xC0
#define _FILL_QU_BASE 0xC2
enum _stat_pt_idx {
_STAT_RX_GOOD_OCTETS = 0,
_STAT_RX_BAD_OCTETS,
_STAT_RX_UC,
_STAT_RX_BC,
_STAT_RX_MC,
_STAT_RX_UNDERSZ,
_STAT_RX_FRAGS,
_STAT_RX_OVERSZ,
_STAT_RX_JABBER,
_STAT_RX_ERR,
_STAT_RX_CRC,
_STAT_RX_FULLDROP,
_STAT_RX_POLICED, /* Unused */
_STAT_TX_OCTETS,
_STAT_TX_UC,
_STAT_TX_BC,
_STAT_TX_MC,
_STAT_TX_PRIQDROP,
_STAT_TX_EARLYDROP,
_STAT_RX_64,
_STAT_RX_65_127,
_STAT_RX_128_255,
_STAT_RX_256_511,
_STAT_RX_512_1023,
_STAT_RX_1024_1536,
_STAT_MAX, /* must be last element */
};
struct edgx_pt_ipo {
u16 cfg0;
u16 fwd;
u16 mirror;
u16 cfg1;
u8 mac[ETH_ALEN];
};
#define _GEN_BASE(_iob) ((_iob) + 0x0)
#define _IPO_BASE(_iob) ((_iob) + 0x8000)
#define _IPO_RBASE(_iob, _rule) (_IPO_BASE(_iob) + (0x20 * (_rule)))
#define _FRAMESIZE_BASE(_iob, idx) (_GEN_BASE(_iob) + 0x40 + (0x02 * (idx)))
#define _FRAMESIZE_MASK (0x7ff)
#define _FRAMESIZE_OVERHEAD (10U)
#define _FIDCFG_REG(_ofs) (0x80 + (_ofs))
static const struct edgx_statinfo _pt_statinfo = {
.feat_id = EDGX_STAT_FEAT_PORT,
.rate_ms = 3000, /* fastest counter in block overwraps every
* 4.2 seconds -> set to 3 seconds
*/
.base = _STAT_PORT_BASE,
.nwords = _STAT_MAX,
};
struct edgx_switchdev_event_work {
struct work_struct work;
struct switchdev_notifier_fdb_info fdb_info;
struct edgx_pt *pt;
unsigned long event;
};
static inline bool is_bridged(struct edgx_pt *pt)
{
return (pt->netdev->priv_flags & IFF_BRIDGE_PORT);
}
static inline struct edgx_pt *net2pt(struct net_device *netdev)
{
return ((struct edgx_pt *)netdev_priv(netdev));
}
struct edgx_link *edgx_net2link(struct net_device *netdev)
{
return (net2pt(netdev)) ? net2pt(netdev)->link : NULL;
}
static inline struct edgx_time *net2time(struct net_device *netdev)
{
return (net2pt(netdev)) ? net2pt(netdev)->time : NULL;
}
static inline struct edgx_br *pt2br(struct edgx_pt *pt)
{
return pt->parent;
}
static inline int edgx_pt_open(struct net_device *netdev)
{
struct edgx_link *lnk = net2pt(netdev)->link;
edgx_link_start(lnk);
return 0;
}
static int edgx_pt_stop(struct net_device *netdev)
{
struct edgx_link *lnk = net2pt(netdev)->link;
edgx_link_stop(lnk);
return 0;
}
static struct edgx_pt_ipo ipo_mgmt[] = {
/* CFG0: Enabled, Compare length = 44bit
* new/preserve priority is set to traffic-class 0,
* will be fixed in ipo_init() as it depends on #queues
* FWD: left empty, will become mgmt-port (or all) upon ipo_init()
* MIRROR: left empty, will become mgmt-port (or all) upon ipo_init()
* may become dedicated mirror-port
* CFG1: Compare MSB first, disable cut-through, DO use IPO-mark
*/
{0xB1, 0x0, 0x0, 0xD000, {0x01, 0x80, 0xC2, 0x00, 0x00, 0x00} },
{0xB1, 0x0, 0x0, 0xD000, {0x01, 0x80, 0xC2, 0x00, 0x00, 0x10} },
/* CFG0: Enabled, Compare length = 48bit
* Used for preemption verification frames which have to be
* received on the corresponding bridge port, and are identified
* by MAC address 00:00:00:00:00:00
* Remaining items as described above.
*/
{0xC1, 0x0, 0x0, 0xD000, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
/* Management entry for 01:80:C2:00:00:2X is only valid if MRP is
* supported (see IEEE 802.1Q-2014, Sect. 10.5, item b.2)
*/
};
/* CFG0: Cmp-len (bits 7-2) = 48bit (full MAC), keep priority
* FWD: 0 now, will be set to mgmt-port upon ipo_init()
* MIRROR: 0 now, may become dedicated mirror-port
* CFG1: MSB-first compare, NO cut-through, NO IPO-mark
*/
static struct edgx_pt_ipo ipo_self = {0x40C1, 0x0, 0x0, 0xD000,
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
/* CFG0: Cmp-len (bits 7-2) = 0 (match all), keep priority
* FWD: 0xFFFF - allow on all ports
* MIRROR: 0 now, may become dedicated mirror-port
* CFG1: MSB-first compare, NO cut-through, NO IPO-mark
*/
static struct edgx_pt_ipo ipo_all = {0x4001, 0xFFFF, 0x0, 0xC000,
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
/* Unused/Disabled IPO entry */
static struct edgx_pt_ipo ipo_null = {0x0, 0x0, 0x0, 0x0,
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
/* We use dedicated entries, so that we know what we need to update, e.g.,
* self MAC or mirroring.
*/
#define _IPO_SELF_ENT ARRAY_SIZE(ipo_mgmt)
#define _IPO_ALL_ENT (_IPO_SELF_ENT + 1)
#define _IPO_NONE_ENT_START (_IPO_ALL_ENT + 1)
#define _IPO_NRULES (16)
#define _IPO_REG_CMD 0x0
#define _IPO_REG_CFG0 0x10
#define _IPO_REG_FWD 0x12
#define _IPO_REG_MIRR 0x14
#define _IPO_REG_CFG1 0x16
#define _IPO_REG_ETH_0 0x18
#define _IPO_REG_ETH_1 0x1A
#define _IPO_REG_ETH_2 0x1C
#define _IPO_CMD_CFG0 (0x1)
#define _IPO_CMD_FWD (0x2)
#define _IPO_CMD_MIRR (0x3)
#define _IPO_CMD_CFG1 (0x4)
#define _IPO_CMD_ETH_0 (0x5)
#define _IPO_CMD_ETH_1 (0x6)
#define _IPO_CMD_ETH_2 (0x7)
#define _IPO_CMD_WRITE (1<<14)
#define _IPO_CMD_READ (0<<14)
#define _IPO_CMD_TRANSFER (1<<15)
static inline void edgx_pt_ipo_set_mac(edgx_io_t *ipo_rbase, u8 *mac)
{
edgx_set16(ipo_rbase, _IPO_REG_ETH_0, 7, 0, mac[0]);
edgx_set16(ipo_rbase, _IPO_REG_ETH_0, 15, 8, mac[1]);
edgx_set16(ipo_rbase, _IPO_REG_ETH_1, 7, 0, mac[2]);
edgx_set16(ipo_rbase, _IPO_REG_ETH_1, 15, 8, mac[3]);
edgx_set16(ipo_rbase, _IPO_REG_ETH_2, 7, 0, mac[4]);
edgx_set16(ipo_rbase, _IPO_REG_ETH_2, 15, 8, mac[5]);
}
static inline void edgx_pt_ipo_init_single(edgx_io_t *ipo_rbase,
struct edgx_pt_ipo *ipo,
u8 entry)
{
u16 reg;
/* Read the value from registers */
edgx_wr16(ipo_rbase, _IPO_REG_CMD,
(entry | _IPO_CMD_READ | _IPO_CMD_TRANSFER));
/* Sleep and then wait until flags are cleared by HW. */
usleep_range(300, 400);
do {
reg = edgx_get16(ipo_rbase, _IPO_REG_CMD, 15, 15);
} while (reg);
edgx_wr16(ipo_rbase, _IPO_REG_CFG0, ipo->cfg0);
edgx_wr16(ipo_rbase, _IPO_REG_FWD, ipo->fwd);
edgx_wr16(ipo_rbase, _IPO_REG_MIRR, ipo->mirror);
edgx_wr16(ipo_rbase, _IPO_REG_CFG1, ipo->cfg1);
edgx_pt_ipo_set_mac(ipo_rbase, ipo->mac);
}
static void edgx_pt_ipo_init(struct edgx_pt *pt, ptid_t mgmt_ptid)
{
unsigned int entry;
edgx_io_t *ipo_rbase;
u16 reg;
u16 mtc = edgx_get_tc_mgmtraffic(pt->parent);
mutex_lock(&pt->reg_lock);
for (entry = 0; entry < ARRAY_SIZE(ipo_mgmt); entry++) {
ipo_rbase = _IPO_BASE(pt->iobase);
edgx_pt_ipo_init_single(ipo_rbase, &ipo_mgmt[entry], entry);
/* write traffic class number for reserved MAC traffic to IPO
* registers:
*/
/* write bit 0 to bit 15 of _IPO_REG_CFG0 */
edgx_set16(ipo_rbase, _IPO_REG_CFG0, 15, 15, (mtc & 0x1));
/* write bit 1 and 2 to bits 12 and 13 of _IPO_REG_CFG0 */
edgx_set16(ipo_rbase, _IPO_REG_CFG0, 13, 12, mtc >> 1);
/* Need to set FWD and MIRROR, so that mgmt frames also arrive
* when in blocking state
*/
edgx_wr16(ipo_rbase, _IPO_REG_FWD, BIT(mgmt_ptid));
edgx_wr16(ipo_rbase, _IPO_REG_MIRR, BIT(mgmt_ptid));
/* Write the values to IP using indirect access */
edgx_wr16(ipo_rbase, _IPO_REG_CMD,
(entry | _IPO_CMD_WRITE | _IPO_CMD_TRANSFER));
/* Sleep and wait until flags are cleared by HW */
usleep_range(300, 400);
do {
reg = edgx_get16(ipo_rbase, _IPO_REG_CMD, 15, 15);
} while (reg);
}
/* Setup individual(self)-MAC-rule for port */
ipo_rbase = _IPO_BASE(pt->iobase);
/* Read values for _IPO_SELF_ENT rule */
edgx_wr16(ipo_rbase, _IPO_REG_CMD,
(_IPO_SELF_ENT |
_IPO_CMD_READ |
_IPO_CMD_TRANSFER));
/* Sleep and wait until flags are cleared by HW */
usleep_range(300, 400);
do {
reg = edgx_get16(ipo_rbase, _IPO_REG_CMD, 15, 15);
} while (reg);
edgx_pt_ipo_init_single(ipo_rbase, &ipo_self, _IPO_SELF_ENT);
edgx_pt_ipo_set_mac(ipo_rbase, pt->netdev->dev_addr);
/* Need to set FWD and MIRROR, so that mgmt frames also arrive
* when port is in blocking state
*/
edgx_wr16(ipo_rbase, _IPO_REG_FWD, BIT(mgmt_ptid));
edgx_wr16(ipo_rbase, _IPO_REG_MIRR, BIT(mgmt_ptid));
edgx_wr16(ipo_rbase, _IPO_REG_CMD,
(_IPO_SELF_ENT |
_IPO_CMD_WRITE |
_IPO_CMD_TRANSFER));
/* Sleep and then wait until flags are cleared by HW */
usleep_range(300, 400);
do {
reg = edgx_get16(ipo_rbase, _IPO_REG_CMD, 15, 15);
} while (reg);
/* Setup all-MAC rule for port */
ipo_rbase = _IPO_BASE(pt->iobase);
/* Read values for _IPO_ALL_ENT rule */
edgx_wr16(ipo_rbase, _IPO_REG_CMD,
(_IPO_ALL_ENT |
_IPO_CMD_READ |
_IPO_CMD_TRANSFER));
/* Sleep and then wait until flags are cleared by HW */
usleep_range(300, 400);
do {
reg = edgx_get16(ipo_rbase, _IPO_REG_CMD, 15, 15);
} while (reg);
edgx_pt_ipo_init_single(ipo_rbase, &ipo_all, _IPO_ALL_ENT);
/* don't allow forwarding to self, no allowed for bridges! */
edgx_set16(ipo_rbase, _IPO_REG_FWD, pt->ptid, pt->ptid, 0);
edgx_wr16(ipo_rbase, _IPO_REG_CMD,
(_IPO_ALL_ENT |
_IPO_CMD_WRITE |
_IPO_CMD_TRANSFER));
/* Sleep and then wait until flags are cleared by HW */
usleep_range(300, 400);
do {
reg = edgx_get16(ipo_rbase, _IPO_REG_CMD, 15, 15);
} while (reg);
/* Clear out the rest using the none-rule */
for (entry = _IPO_NONE_ENT_START; entry < _IPO_NRULES; entry++) {
ipo_rbase = _IPO_BASE(pt->iobase);
/* Read values for entry */
edgx_wr16(ipo_rbase, _IPO_REG_CMD,
(entry | _IPO_CMD_READ | _IPO_CMD_TRANSFER));
/* Sleep and then wait until flags are cleared by HW */
usleep_range(300, 400);
do {
reg = edgx_get16(ipo_rbase, _IPO_REG_CMD, 15, 15);
} while (reg);
edgx_pt_ipo_init_single(ipo_rbase, &ipo_null, entry);
/* Write values for entry rule */
edgx_wr16(ipo_rbase, _IPO_REG_CMD,
(entry | _IPO_CMD_WRITE | _IPO_CMD_TRANSFER));
/* Sleep and then wait until flags are cleared by HW */
usleep_range(300, 400);
do {
reg = edgx_get16(ipo_rbase, _IPO_REG_CMD, 15, 15);
} while (reg);
}
mutex_unlock(&pt->reg_lock);
}
static ptid_t edgx_pt_ipo_get_mirror(struct edgx_pt *pt)
{
u16 reg;
ptid_t mgmt_ptid = edgx_com_get_mgmt_ptid(edgx_br_get_com(pt2br(pt)));
edgx_io_t *ipo_rbase = _IPO_BASE(pt->iobase);
u16 mirr_cfg;
mutex_lock(&pt->reg_lock);
edgx_wr16(ipo_rbase, _IPO_REG_CMD,
(_IPO_SELF_ENT | _IPO_CMD_READ | _IPO_CMD_TRANSFER));
/* Sleep and then wait until flags are cleared by HW */
usleep_range(300, 400);
do {
reg = edgx_get16(ipo_rbase, _IPO_REG_CMD, 15, 15);
} while (reg);
mirr_cfg = edgx_rd16(ipo_rbase, _IPO_REG_MIRR);
mutex_unlock(&pt->reg_lock);
mirr_cfg = mirr_cfg ^ BIT(mgmt_ptid);
return (mirr_cfg) ? ffs(mirr_cfg) - 1 : -1;
}
static int edgx_pt_ipo_set_mirror(struct edgx_pt *pt, ptid_t mirr_ptid)
{
unsigned int i;
ptid_t mgmt_ptid = edgx_com_get_mgmt_ptid(edgx_br_get_com(pt2br(pt)));
ptid_t mirr_ptid_int = mirr_ptid - 1; // internal port id is one less than external port id
u16 mirr_cfg = BIT(mgmt_ptid) | ((mirr_ptid_int < 0) ? 0 : BIT(mirr_ptid_int));
u16 reg;
if (mirr_ptid_int == edgx_pt_get_id(pt) || mirr_ptid_int == mgmt_ptid) {
edgx_pt_err(pt, "Cannot mirror management port or to self.\n");
return -EINVAL;
}
for (i = _IPO_SELF_ENT; i < _IPO_NRULES; i++) {
edgx_io_t *ipo_rbase = _IPO_BASE(pt->iobase);
mutex_lock(&pt->reg_lock);
edgx_wr16(ipo_rbase, _IPO_REG_CMD,
(i | _IPO_CMD_READ | _IPO_CMD_TRANSFER));
/* Sleep and then wait until flags are cleared by HW */
usleep_range(300, 400);
do {
reg = edgx_get16(ipo_rbase, _IPO_REG_CMD, 15, 15);
} while (reg);
edgx_wr16(ipo_rbase, _IPO_REG_MIRR, mirr_cfg);
edgx_wr16(ipo_rbase, _IPO_REG_CMD,
(i | _IPO_CMD_WRITE | _IPO_CMD_TRANSFER));
/* Sleep and then wait until flags are cleared by HW */
usleep_range(300, 400);
do {
reg = edgx_get16(ipo_rbase, _IPO_REG_CMD, 15, 15);
} while (reg);
mutex_unlock(&pt->reg_lock);
}
return 0;
}
void edgx_pt_set_pvid(struct edgx_pt *pt, u16 vid)
{
/* Set both registers; one is PVID, the other one also assigns priority-
* tagged frames to the PVID.
*/
edgx_set16(_GEN_BASE(pt->iobase), 0x10, 11, 0, vid);
edgx_set16(_GEN_BASE(pt->iobase), 0x12, 11, 0, vid);
}
void edgx_pt_clear_pvid(struct edgx_pt *pt)
{
edgx_pt_set_pvid(pt, _PVID_NONE);
}
u16 edgx_pt_get_pvid(struct edgx_pt *pt)
{
return edgx_get16(_GEN_BASE(pt->iobase), 0x10, 11, 0);
}
static int edgx_pt_get_dflt_pcp(struct edgx_pt *pt)
{
return edgx_get16(_GEN_BASE(pt->iobase), 0x10, 14, 12);
}
static int edgx_pt_set_dflt_pcp(struct edgx_pt *pt, unsigned int prio)
{
if (prio > 7)
return -EINVAL;
edgx_set16(_GEN_BASE(pt->iobase), 0x10, 14, 12, prio);
return 0;
}
static ssize_t flush_tree_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct edgx_pt *pt = edgx_dev2pt(dev);
mstid_t mstid;
if (kstrtou16(buf, 10, &mstid))
return -EINVAL;
if (edgx_br_vlan_flush_mstpt(edgx_br_get_vlan(pt2br(pt)),
mstid, pt->ptid))
return -EINVAL;
return count;
}
static ssize_t tree_port_state_read(struct file *filp, struct kobject *kobj,
struct bin_attribute *bin_attr, char *buf,
loff_t ofs, size_t count)
{
struct edgx_pt *pt = edgx_dev2pt(kobj_to_dev(kobj));
loff_t idx;
u8 ptstate;
if (edgx_sysfs_tbl_params(ofs, count, sizeof(unsigned int), &idx) ||
edgx_br_vlan_get_mstpt_state(edgx_br_get_vlan(pt2br(pt)),
(mstid_t)idx, pt->ptid, &ptstate))
return 0;
*((unsigned int *)buf) = ptstate;
return count;
}
static ssize_t tree_port_state_write(struct file *filp, struct kobject *kobj,
struct bin_attribute *bin_attr, char *buf,
loff_t ofs, size_t count)
{
struct edgx_pt *pt = edgx_dev2pt(kobj_to_dev(kobj));
loff_t idx;
if (edgx_sysfs_tbl_params(ofs, count, sizeof(unsigned int), &idx) ||
edgx_br_vlan_set_mstpt_state(edgx_br_get_vlan(pt2br(pt)),
(mstid_t)idx, pt, *((u8 *)buf)))
return -EINVAL;
return count;
}
EDGX_DEV_ATTR_WO(flush_tree, "flushTree");
EDGX_BIN_ATTR_RW(tree_port_state, "treePortState",
EDGX_MAX_MSTID * sizeof(unsigned int));
static struct attribute *ieee8021_mstp_attrs[] = {
&dev_attr_flush_tree.attr,
NULL,
};
static struct bin_attribute *ieee8021_mstp_binattrs[] = {
&bin_attr_tree_port_state,
NULL,
};
static struct attribute_group ieee8021_mstp_group = {
.name = "ieee8021Mstp",
.attrs = ieee8021_mstp_attrs,
.bin_attrs = ieee8021_mstp_binattrs,
};
static ssize_t num_tcs_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct edgx_pt *pt = edgx_dev2pt(dev);
return scnprintf(buf, PAGE_SIZE, "%u\n",
edgx_br_get_generic(pt->parent, BR_GX_QUEUES));
}
static ssize_t dflt_usr_prio_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct edgx_pt *pt = edgx_dev2pt(dev);
return scnprintf(buf, PAGE_SIZE, "%u\n", edgx_pt_get_dflt_pcp(pt));
}
static ssize_t dflt_usr_prio_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct edgx_pt *pt = edgx_dev2pt(dev);
unsigned int prio;
int r = kstrtouint(buf, 10, &prio);
if (r)
return r;
return (edgx_pt_set_dflt_pcp(pt, prio)) ? -EINVAL : count;
}
static ssize_t external_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct edgx_pt *pt = edgx_dev2pt(dev);
return scnprintf(buf, PAGE_SIZE, "%u\n",
edgx_link_is_external(pt->link));
}
static ssize_t port_type_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
return scnprintf(buf, PAGE_SIZE, "2\n"); /* customerVlanPort */
}
EDGX_DEV_ATTR_RO(num_tcs, "portNumTrafficClasses");
EDGX_DEV_ATTR_RW(dflt_usr_prio, "portDefaultUserPriority");
EDGX_DEV_ATTR_RO(external, "portExternal");
EDGX_DEV_FCT_ATTR_RO(aft, edgx_sysfs_one, "portAcceptableFrameTypes");
EDGX_DEV_FCT_ATTR_RO(eif, edgx_sysfs_true, "portEnableIngressFiltering");
EDGX_DEV_FCT_ATTR_RO(tag, edgx_sysfs_true, "portTaggingCapable");
EDGX_DEV_FCT_ATTR_RO(cfgft, edgx_sysfs_false,
"portConfigurableAcceptableFrameTypes");
EDGX_DEV_FCT_ATTR_RO(inf, edgx_sysfs_true, "portIngressFilteringCapable");
EDGX_DEV_FCT_ATTR_RO(cv, edgx_sysfs_true, "portTypeCapCustomerVlan");
EDGX_DEV_FCT_ATTR_RO(pn, edgx_sysfs_false, "portTypeCapProviderNetwork");
EDGX_DEV_FCT_ATTR_RO(cn, edgx_sysfs_false, "portTypeCapCustomerNetwork");
EDGX_DEV_FCT_ATTR_RO(ce, edgx_sysfs_false, "portTypeCapCustomerEdge");
EDGX_DEV_FCT_ATTR_RO(cb, edgx_sysfs_false, "portTypeCapCustomerBackbone");
EDGX_DEV_FCT_ATTR_RO(vi, edgx_sysfs_false, "portTypeCapVirtualInstance");
EDGX_DEV_FCT_ATTR_RO(db, edgx_sysfs_true, "portTypeCapDBridge");
EDGX_DEV_FCT_ATTR_RO(rca, edgx_sysfs_false, "portTypeCapRemoteCustomerAccess");
EDGX_DEV_FCT_ATTR_RO(sf, edgx_sysfs_false, "portTypeCapStationFacing");
EDGX_DEV_FCT_ATTR_RO(ua, edgx_sysfs_false, "portTypeCapUplinkAccess");
EDGX_DEV_FCT_ATTR_RO(ur, edgx_sysfs_false, "portTypeCapUplinkRelay");
EDGX_DEV_FCT_ATTR_RO(pt, port_type, "portType");
static void get_tc_prio_params(int idx, int type, size_t *reg_ofs, int *bithi,
int *bitlo)
{
if (idx < SZ_4) {
if (type == _TYPE_PRIO_REGEN)
*reg_ofs = _PRIO_REGEN_LO;
else if (type == _TYPE_QUEUE_TBL)
*reg_ofs = _QUEUE_TBL_LO;
*bithi = idx * SZ_4 + 3;
*bitlo = idx * SZ_4;
} else {
if (type == _TYPE_PRIO_REGEN)
*reg_ofs = _PRIO_REGEN_HI;
else if (type == _TYPE_QUEUE_TBL)
*reg_ofs = _QUEUE_TBL_HI;
*bithi = (idx - 4) * SZ_4 + 3;
*bitlo = (idx - 4) * SZ_4;
}
}
static ssize_t prio_regen_tbl_write(struct file *filp, struct kobject *kobj,
struct bin_attribute *bin_attr,
char *buf, loff_t ofs, size_t count)
{
/* parameter buf contains value of priority
* parameter ofs contains value of PCP
*/
loff_t idx = 0;
struct edgx_pt *pt = edgx_dev2pt(kobj_to_dev(kobj));
size_t reg_ofs;
int bithi, bitlo;
if (edgx_sysfs_tbl_params(ofs, count, sizeof(u8), &idx) ||
idx > _MAX_PRIO_VAL ||
((u8 *)buf)[0] > _MAX_PRIO_VAL)
return -EINVAL;
get_tc_prio_params(idx, _TYPE_PRIO_REGEN, ®_ofs, &bithi, &bitlo);
edgx_set16(pt->iobase, reg_ofs, bithi, bitlo, ((u8 *)buf)[0]);
return count;
}
static ssize_t traffic_class_tbl_write(struct file *filp, struct kobject *kobj,
struct bin_attribute *bin_attr,
char *buf, loff_t ofs, size_t count)
{
/* parameter buf contains value of traffic class
* parameter ofs contains value of priority
*/
loff_t idx = 0;
struct edgx_pt *pt = edgx_dev2pt(kobj_to_dev(kobj));
size_t reg_ofs;
int bithi, bitlo;
if (edgx_sysfs_tbl_params(ofs, count, sizeof(u8), &idx) ||
idx > _MAX_PRIO_VAL ||
((u8 *)buf)[0] > (edgx_br_get_generic(edgx_pt_get_br(pt),
BR_GX_QUEUES) - 1))
return -EINVAL;
get_tc_prio_params(idx, _TYPE_QUEUE_TBL, ®_ofs, &bithi, &bitlo);
edgx_set16(pt->iobase, reg_ofs, bithi, bitlo, ((u8 *)buf)[0]);
return count;
}
static ssize_t prio_regen_tbl_read(struct file *filp, struct kobject *kobj,
struct bin_attribute *bin_attr,
char *buf, loff_t ofs, size_t count)
{
/* parameter buf contains value of priority
* parameter ofs contains value of PCP
*/
loff_t idx = 0;
struct edgx_pt *pt = edgx_dev2pt(kobj_to_dev(kobj));
size_t reg_ofs;
int bithi, bitlo;
if (edgx_sysfs_tbl_params(ofs, count, sizeof(u8), &idx) ||
idx > _MAX_PRIO_VAL)
return -EINVAL;
get_tc_prio_params(idx, _TYPE_PRIO_REGEN, ®_ofs, &bithi, &bitlo);
((u8 *)buf)[0] = edgx_get16(pt->iobase, reg_ofs, bithi, bitlo);
edgx_dbg("%s: PCP: %d, priority: %d, port: %s\n", __func__, (u8)idx,
edgx_get16(pt->iobase, reg_ofs, bithi, bitlo),
edgx_pt_get_name(pt));
return count;
}
static ssize_t traffic_class_tbl_read(struct file *filp, struct kobject *kobj,
struct bin_attribute *bin_attr,
char *buf, loff_t ofs, size_t count)
{
/* parameter buf contains value of traffic class
* parameter ofs contains value of priority
*/
loff_t idx = 0;
struct edgx_pt *pt = edgx_dev2pt(kobj_to_dev(kobj));
size_t reg_ofs;
int bithi, bitlo;
if (edgx_sysfs_tbl_params(ofs, count, sizeof(u8), &idx) ||
idx > _MAX_PRIO_VAL)
return -EINVAL;
get_tc_prio_params(idx, _TYPE_QUEUE_TBL, ®_ofs, &bithi, &bitlo);
((u8 *)buf)[0] = edgx_get16(pt->iobase, reg_ofs, bithi, bitlo);
edgx_dbg("%s: priority: %d, traffic class: %d, port: %s\n",
__func__, (u8)idx,
edgx_get16(pt->iobase, reg_ofs, bithi, bitlo),
edgx_pt_get_name(pt));
return count;
}
EDGX_BIN_ATTR_RW(prio_regen_tbl, "portUserPriorityRegenTable",
EDGX_BR_NUM_PCP * sizeof(u8));
EDGX_BIN_ATTR_RW(traffic_class_tbl, "portTrafficClassTable",
EDGX_BR_NUM_PCP * sizeof(u8));
static struct attribute *ieee8021_bridge_attrs[] = {
&dev_attr_num_tcs.attr,
&dev_attr_dflt_usr_prio.attr,
&dev_attr_external.attr,
&dev_attr_aft.attr,
&dev_attr_eif.attr,
&dev_attr_tag.attr,
&dev_attr_cfgft.attr,
&dev_attr_inf.attr,
&dev_attr_cv.attr,
&dev_attr_pn.attr,
&dev_attr_cn.attr,
&dev_attr_ce.attr,
&dev_attr_cb.attr,
&dev_attr_vi.attr,
&dev_attr_db.attr,
&dev_attr_rca.attr,
&dev_attr_sf.attr,
&dev_attr_ua.attr,
&dev_attr_ur.attr,
&dev_attr_pt.attr,
NULL,
};
static struct bin_attribute *ieee8021_bridge_binattrs[] = {
&bin_attr_prio_regen_tbl,
&bin_attr_traffic_class_tbl,
NULL
};
static struct attribute_group ieee8021_bridge_group = {
.name = "ieee8021Bridge",
.attrs = ieee8021_bridge_attrs,
.bin_attrs = ieee8021_bridge_binattrs,
};
static ssize_t mirror_port_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct edgx_pt *pt = edgx_dev2pt(dev);
return scnprintf(buf, PAGE_SIZE, "%d\n",
edgx_pt_ipo_get_mirror(pt));
}
static ssize_t mirror_port_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct edgx_pt *pt = edgx_dev2pt(dev);
ptid_t mirror_pt;
int r;
if (kstrtoint(buf, 10, &mirror_pt))
return -EINVAL;
r = edgx_pt_ipo_set_mirror(pt, mirror_pt);
return (r) ? r : count;
}
static ssize_t cutthrough_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct edgx_pt *pt = edgx_dev2pt(dev);
return scnprintf(buf, PAGE_SIZE, "%u\n",
edgx_get16(_GEN_BASE(pt->iobase), 0x0, 15, 15));
}
static ssize_t cutthrough_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct edgx_pt *pt = edgx_dev2pt(dev);
bool en;
if (kstrtobool(buf, &en))
return -EINVAL;
edgx_wr16(_GEN_BASE(pt->iobase), 0x1a, (en) ? 0xff : 0x0);
edgx_set16(_GEN_BASE(pt->iobase), 0x0, 15, 15, (en) ? 1 : 0);
return count;
}
EDGX_DEV_ATTR_RW(mirror_port, "mirrorPort");
EDGX_DEV_ATTR_RW(cutthrough, "cutThrough");
static struct attribute *edgex_ext_attrs[] = {
&dev_attr_mirror_port.attr,
&dev_attr_cutthrough.attr,
NULL,
};
static struct attribute_group edgex_ext_group = {
.name = "edgex-ext",
.attrs = edgex_ext_attrs,
};
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 3, 0)
static int edgx_pt_attr_get(struct net_device *dev,
struct switchdev_attr *attr)
{
struct edgx_pt *pt = net2pt(dev);
int err = 0;
switch (attr->id) {
case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
attr->u.ppid.id_len = sizeof(ETH_ALEN);
memcpy(&attr->u.ppid.id, edgx_br_get_mac(pt2br(pt)),
attr->u.ppid.id_len);
break;
case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS:
attr->u.brport_flags = _BRPT_FLAGS;
break;
case SWITCHDEV_ATTR_ID_PORT_STP_STATE:
err = edgx_br_vlan_get_mstpt_state(edgx_br_get_vlan(pt2br(pt)),
EDGX_CIST_MSTID, pt->ptid,
&attr->u.stp_state);
break;
case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME:
edgx_pt_info(pt, "getting ageing time\n");
attr->u.ageing_time = edgx_br_ageing_get(pt2br(pt));
break;
default:
return -EOPNOTSUPP;
}
return err;
}
#endif
static int edgx_pt_attr_set(struct net_device *dev,
const struct switchdev_attr *attr,
struct switchdev_trans *trans)
{
struct edgx_pt *pt = net2pt(dev);
int err = 0;
switch (attr->id) {
case SWITCHDEV_ATTR_ID_PORT_STP_STATE:
err = edgx_br_vlan_set_mstpt_state(edgx_br_get_vlan(pt2br(pt)),
EDGX_CIST_MSTID, pt,
attr->u.stp_state);
break;
case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME:
err = edgx_br_ageing_set(pt2br(pt), attr->u.ageing_time);
break;
default:
return -EOPNOTSUPP;
}
return err;
}
static int edgx_pt_obj_add(struct net_device *dev,
const struct switchdev_obj *obj,
struct switchdev_trans *trans)
{
struct edgx_pt *pt = net2pt(dev);
int err = 0;
if (switchdev_trans_ph_prepare(trans))
return 0;
switch (obj->id) {
case SWITCHDEV_OBJ_ID_PORT_VLAN:
if (!is_bridged(pt)) {
edgx_pt_err(pt, "Cannot add VID(s) to unbridged port\n");
return -EINVAL;
}
err = edgx_br_vlan_add_pt(edgx_br_get_vlan(pt2br(pt)),
SWITCHDEV_OBJ_PORT_VLAN(obj), pt);
break;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0)
case SWITCHDEV_OBJ_ID_PORT_MDB:
case SWITCHDEV_OBJ_ID_HOST_MDB: {
/* Ignore MDB objects to avoid kernel warning. */
break;
}
#endif
default:
err = -EOPNOTSUPP;
}
return err;
}
static int edgx_pt_obj_del(struct net_device *dev,
const struct switchdev_obj *obj)
{
struct edgx_pt *pt = net2pt(dev);
int err = 0;
switch (obj->id) {
case SWITCHDEV_OBJ_ID_PORT_VLAN:
if (!is_bridged(pt)) {
edgx_pt_err(pt, "Cannot delete VID from unbridged port\n");
return -EINVAL;
}
err = edgx_br_vlan_del_pt(edgx_br_get_vlan(pt2br(pt)),
SWITCHDEV_OBJ_PORT_VLAN(obj), pt);
break;
default:
err = -EOPNOTSUPP;
}
return err;
}
void edgx_pt_set_fid_fwd_state(struct edgx_pt *pt, fid_t fid, u8 ptstate)
{
u16 hwstate;
u64 ofs = fid;
int bitlo;
switch (ptstate) {
case BR_STATE_FORWARDING:
hwstate = _PT_STP_FWD;
break;
case BR_STATE_LEARNING:
hwstate = _PT_STP_LEARN;