diff --git a/CHANGELOG.md b/CHANGELOG.md index be1b7bf..6ff7c14 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,10 @@ This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). +## [1.4.2] - 2022-03-02 +- updates to trap handler +- fixes to instruction constants + ## [1.4.1] - 2022-02-28 - fix bug with configuration yaml CLI - update colorlog requirement diff --git a/setup.cfg b/setup.cfg index 7b5e700..ed8351e 100644 --- a/setup.cfg +++ b/setup.cfg @@ -1,5 +1,5 @@ [bumpversion] -current_version = 1.4.1 +current_version = 1.4.2 commit = True tag = True diff --git a/setup.py b/setup.py index fb414a0..f430588 100644 --- a/setup.py +++ b/setup.py @@ -29,7 +29,7 @@ def read_requires(): setup( name='uatg', - version='1.4.1', + version='1.4.2', description="UATG - Micro-Architecture (µArch) Tests Generator", long_description=readme + '\n\n', classifiers=[ diff --git a/uatg/__init__.py b/uatg/__init__.py index be4c380..31c1963 100644 --- a/uatg/__init__.py +++ b/uatg/__init__.py @@ -3,4 +3,4 @@ __author__ = """InCore Semiconductors Pvt Ltd""" __email__ = 'neelgala@incoresemi.com' -__version__ = '1.4.1' +__version__ = '1.4.2' diff --git a/uatg/env/arch_test.h b/uatg/env/arch_test.h index 2f94e2e..0c6206c 100644 --- a/uatg/env/arch_test.h +++ b/uatg/env/arch_test.h @@ -172,13 +172,45 @@ bne t3, a0, unintended_trap_handler intended_trap_handler: + + // instruction address misaligned + li t3, 0 + beq t3, t0, instruction_misaligned_handler + + // breakpoint + li t3, 3 + beq t3, t0, increment_pc + + // load access fault + li t3, 5 + beq t3, t0, increment_pc + + // store/AMO misaligned + li t3, 6 + beq t3, t0, increment_pc + + // store access fault + li t3, 7 + beq t3, t0, increment_pc + + // e-call from M + li t3, 11 + beq t3, t0, increment_pc #ifdef s_u_mode_test - // ecall from Supervisor Mode + // ecall from Supervisor Mode. rets to Machine mode li t3, 9 beq t3, t0, supervisor_to_machine_ecall_handler // if t0 == 9, the trap is due to an ecall from S + // ecall from user mode, rets to supervisor mode li t3, 8 beq t3, t0, user_to_supervisor_ecall_handler // if t0 == 8, the trap is due to an ecall from U + // load page fault + li t3, 13 + beq t3, t0, increment_pc + // store/AMO page fault + li t3, 15 + beq t3, t0, increment_pc + #endif j unintended_trap_handler @@ -219,6 +251,7 @@ // for all other cause values restore and exit handler j restore_and_exit_trap +instruction_misaligned_handler: store_misaligned_handler: load_misaligned_handler: // load the lowest byte of the instruction into t3. address of instruction in @@ -226,18 +259,16 @@ // we then follow the same stuff we do for illegal illegal_handler: - +increment_pc: andi t1, t1, 0x3 - addi t4, x0, 3 - beq t4, t1, four_byte + addi t4, x0, 2 + beq t4, t1, two_byte // checks if C is enabled in MISA - csrr t6, CSR_MISA - slli t6, t6, (XLEN-4) - srli t6, t6, (XLEN-1) - beq t6, x0, four_byte - - j two_byte + // csrr t6, CSR_MISA + // slli t6, t6, (XLEN-4) + // srli t6, t6, (XLEN-1) + // beq t6, x0, four_byte four_byte: addi t2, t2, 0x4 @@ -649,6 +680,14 @@ RVTEST_SIGUPD(swreg,destreg,offset) ) //-------------------------------mbox macros----------------------------------- +//Test for mbox instructions with compressed instructions (WAR dependecies with mul(32) followed by compressed(16) instruction) +#define MBOX_COMPRESSED_RR_OP(rand_inst, inst, reg1, reg2, reg3, destreg1, correctval, val1, val2, val3, swreg, offset, code...) \ + LI (reg1, val1);\ + LI (reg2, val2);\ + LI (reg3, val3);\ + code;\ + RVTEST_SIGUPD(swreg,destreg1,offset) + //Tests for Mbox instructions with reg reg operand(add-reg and shift-reg) #define MBOX_TEST_RR_OP(inst, inst1, reg1, reg2, reg3, destreg, correctval, val1, val2, val3, swreg, offset, testreg) \ TEST_CASE(testreg, destreg, correctval, swreg, offset, \ diff --git a/uatg/instruction_constants.py b/uatg/instruction_constants.py index dcbe622..2daca85 100644 --- a/uatg/instruction_constants.py +++ b/uatg/instruction_constants.py @@ -126,12 +126,13 @@ # integer constant generation instructions 'reg-const': ['c.li', 'c.lui'], # integer register immediate instructions - 'reg-imm': ['c.addi'], + 'rv32-reg-imm': ['c.addi'], 'rv64-reg-imm': ['c.addiw'], 'rv128-reg-imm': ['c.addiw'], # integer register register operations 'reg-reg': ['c.mv', 'c.add'], - 'reg-regCA': ['c.and', 'c.or', 'c.xor', 'c.sub'], + 'rv32-reg-regCA': ['c.and', 'c.or', 'c.xor', 'c.sub'], + 'rv64-reg-regCA': ['c.and', 'c.or', 'c.xor', 'c.sub'], 'rv64-regCA': ['c.addw', 'c.subw'], 'rv128-regCA': ['c.addw', 'c.subw'] } diff --git a/uatg/utils.py b/uatg/utils.py index 434f101..2ec9b4e 100644 --- a/uatg/utils.py +++ b/uatg/utils.py @@ -881,7 +881,15 @@ def dump_makefile(isa, link_path, test_path, test_name, env_path, work_dir, def setup_pages(page_size=4096, paging_mode='sv39', valid_ll_pages=64, - mode='machine'): + mode='machine', + valid=True, + read=True, + write=True, + execute=True, + user=True, + globl=True, + access=True, + dirty=True): """ creates pagetables to run tests in User and Supervisor modes Currently works with the sv39 virtual memory addressing. @@ -943,15 +951,15 @@ def setup_pages(page_size=4096, base_address = 0x80000000 # all bits other than U bit will be set by default - valid_bit = 0x01 - read_bit = 0x02 - write_bit = 0x04 - execute_bit = 0x08 - u_bit_s = 0x00 - u_bit_u = 0x10 - global_bit = 0x20 - access_bit = 0x40 - dirty_bit = 0x80 + valid_bit = 0x01 if valid else 0x00 + read_bit = 0x02 if read else 0x00 + write_bit = 0x04 if write else 0x00 + execute_bit = 0x08 if execute else 0x00 + u_bit_s = 0x00 if user else 0x00 + u_bit_u = 0x10 if user else 0x00 + global_bit = 0x20 if globl else 0x00 + access_bit = 0x40 if access else 0x00 + dirty_bit = 0x80 if dirty else 0x00 ll_entries_s = '' ll_entries_u = ''