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consider adding SB_RGBA_DRV PWM verilog examples #525
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That is actually the example design in hdl/verilog/blink, hdl/vhdl/blink and hdl/mixed/blink.
Mixed examples are a combination of those: having the counter in one language and the instantiation of the SB_RGBA_DRV in the other. The resulting color cycles are not exactly the same, though, because we did not necessarily care about using exactly the same counter size/period. |
Sorry for the lack of precision I was referring to driving the PWM in a pattern similar to https://github.com/im-tomu/fomu-workshop/blob/master/riscv-blink/src/main.c#L9 rather than blinking full blue, full red, full green at |
Note that bits 25, 24 and 23 compose a 3 bit word with I just run the hdl/vhdl/blink example on my Fomu and the sequence is: off (black), blue, red, magenta, green, cyan, yellow, all (white). Given said that, I think it would be interesting to have this better explained in the docs for the less experienced HDL users. It would also be nice to have some more creative examples that show how to get other colour effects. |
Oh yes, sorry for the miss-understanding, what I meant was that it blinks red, blue and green with between 100% duty cycle and 0% duty cycle at consecutive 2^ interval (causing the 3 components to get mixed as you described), I'd be interesting to provide examples that modulate the PWM duty cycle to get access to more colors. |
It would be nice to show how to drive
RGB0PWM
RGB1PWM
RGB2PWM
using a clock divider, so achieve the same color cycling effect as therisc-v
sample.The text was updated successfully, but these errors were encountered: