forked from nvmecompliance/dnvme
-
Notifications
You must be signed in to change notification settings - Fork 0
/
dnvme_sts_chk.h
300 lines (266 loc) · 8.25 KB
/
dnvme_sts_chk.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
/*
* NVM Express Compliance Suite
* Copyright (c) 2011, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
*/
#ifndef _DNVME_STS_CHK_H_
#define _DNVME_STS_CHK_H_
#include "dnvme_reg.h"
/**
* @def PCI_DEVICE_STATUS
* define the offset for STS register
* from the start of PCI config space as specified in the
* NVME_Comliance 1.0b. offset 06h:STS - Device status.
* This register has error status for NVME PCI Exress
* Card. After reading data from this reagister, the driver
* will identify if any error is set during the operation and
* report as kernel alert message.
*/
#define PCI_DEVICE_STATUS 0x6
/**
* @def DEV_ERR_MASK
* The bit positions that are set in this 16 bit word
* implies that the error is defined for those positions in
* STS register. The bits that are 0 are non error positions.
*/
#define DEV_ERR_MASK 0xB100
/**
* @def DPE
* This bit position indicates data parity error.
* Set to 1 by h/w when the controller detects a
* parity error on its interface.
*/
#define DPE 0x8000
/**
* @def DPD
* This bit position indicates Master data parity error.
* Set to 1 by h/w if parity error is set or parity
* error line is asserted and parity error response bit
* in CMD.PEE is set to 1.
*/
#define DPD 0x0100
/**
* @def RMA
* This bit position indicates Received Master Abort.
* Set to 1 by h/w if when the controller receives a
* master abort to a cycle it generated.
*/
#define RMA 0x2000
/**
* @def RTA
* This bit position indicates Received Target Abort.
* Set to 1 by h/w if when the controller receives a
* target abort to a cycle it generated.
*/
#define RTA 0x1000
/**
* @def CL_MASK
* This bit position indicates Capabilities List of the controller
* The controller should support the PCI Power Management cap as a
* minimum.
*/
#define CL_MASK 0x0010
/**
* @def NEXT_MASK
* This indicates the location of the next capability item
* in the list.
*/
#define NEXT_MASK 0xFF00
#define AER_ERR_MASK 0x20000
/**
* @def PMCAP_ID
* This bit indicates if the pointer leading to this position
* is a PCI power management capability.
*/
#define PMCAP_ID 0x1
/**
* @def MSICAP_ID
* This bit indicates if the pointer leading to this position
* is a capability.
*/
#define MSICAP_ID 0x5
/**
* @def MSIXCAP_ID
* This bit indicates if the pointer leading to this position
* is a capability.
*/
#define MSIXCAP_ID 0x11
/**
* @def PXCAP_ID
* This bit indicates if the pointer leading to this position
* is a capability.
*/
#define PXCAP_ID 0x10
/**
* PCI Express Device Status- PXDS
* The below enums are for PCI express device status reister
* individual status bits and offset position.
*/
enum {
NVME_PXDS_CED = 0x1 << 0, /* Correctable Error */
NVME_PXDS_NFED = 0x1 << 1, /* Non Fatal Error */
NVME_PXDS_FED = 0x1 << 2, /* Fatal Error */
NVME_PXDS_URD = 0x1 << 3, /* Unsupported Request*/
NVME_PXDS_APD = 0x1 << 4, /* AUX Power */
NVME_PXDS_TP = 0x1 << 5, /* Transactions Pending */
NVME_PXDS_RSVD = 0xFFE0, /* Reserved Bits in PXDS */
NVME_PXCAP_PXDS = 0xA, /* Device Status offset from PXCAP */
};
/**
* @def AERCAP_ID
* This bit indicates if the pointer leading to this position
* is a capability.
*/
#define AERCAP_ID 0x0001
/**
* enums for bit positions specified in NVME Controller Status
* offset 0x1Ch CSTS register.
*/
enum {
NVME_CSTS_SHST = 0x3,
NVME_CSTS_SHST_MASK = 0xC,
NVME_CSTS_RSVD = 0xF,
};
/**
* enums for bit positions specified in NVME controller status
* offset 1C CSTS in bits 02:03
*/
enum {
NVME_CSTS_NRML_OPER = 0x0,
NVME_CSTS_SHT_OCC = 0x1,
NVME_CSTS_SHT_COMP = 0x2,
NVME_CSTS_SHT_RSVD = 0x3,
};
/**
* enums for capability version indicated in the AER capability ID
* Offset AERCAP:AERID
*/
enum {
NVME_AER_CVER = 0x2,
};
/**
* enums for Advanced Error reporting Status and Mask Registers offsets
*/
enum {
NVME_AERUCES_OFFSET = 0x4,
NVME_AERUCEM_OFFSET = 0x8,
NVME_AERUCESEV_OFFSET = 0xC,
NVME_AERCS_OFFSET = 0x10,
NVME_AERCM_OFFSET = 0x14,
NVME_AERCC_OFFSET = 0x14,
};
/**
* enums for AER Uncorrectable Error Status and Mask bits.
* The bit positions for status and Mask are same in the NVME Spec 1.0b
* so here we have only this bit positions defined for both AERUCES
* and AERUCEM, mask register.
*/
enum {
NVME_AERUCES_RSVD = 0xFC00002F,
NVME_AERUCES_DLPES = 0x1 << 4,
NVME_AERUCES_PTS = 0x1 << 12,
NVME_AERUCES_FCPES = 0x1 << 13,
NVME_AERUCES_CTS = 0x1 << 14,
NVME_AERUCES_CAS = 0x1 << 15,
NVME_AERUCES_UCS = 0x1 << 16,
NVME_AERUCES_ROS = 0x1 << 17,
NVME_AERUCES_MTS = 0x1 << 18,
NVME_AERUCES_ECRCES = 0x1 << 19,
NVME_AERUCES_URES = 0x1 << 20,
NVME_AERUCES_ACSVS = 0x1 << 21,
NVME_AERUCES_UIES = 0x1 << 22,
NVME_AERUCES_MCBTS = 0x1 << 23,
NVME_AERUCES_AOEBS = 0x1 << 24,
NVME_AERUCES_TPBES = 0x1 << 25,
};
/**
* enums for AER Correctable Error Status and Mask bits.
* The bit positions for status and Mask are same in the NVME Spec 1.0b
* so here we have only this bit positions defined for both AERCS
* and AERCEM, mask register.
*/
enum {
NVME_AERCS_RSVD = 0xFFFF0E3E,
NVME_AERCS_HLOS = 0x1 << 15,
NVME_AERCS_CIES = 0x1 << 14,
NVME_AERCS_ANFES = 0x1 << 13,
NVME_AERCS_RTS = 0x1 << 12,
NVME_AERCS_RRS = 0x1 << 8,
NVME_AERCS_BDS = 0x1 << 7,
NVME_AERCS_BTS = 0x1 << 6,
NVME_AERCS_RES = 0x1 << 0,
};
/**
* device_status_pci function returns the device status of
* the PCI Device status register set in STS register. The offset for this
* register is 0x06h as specified in NVME Express 1.0b spec.
* @param device_data
* @return SUCCESS or FAIL
*/
int device_status_pci(u16 device_data);
/**
* device_status_next function checks if the next capability of the NVME
* Express device exits and if it exists then gets its status.
* @param pdev
* @return SUCCESS or FAIL
*/
int device_status_next(struct pci_dev *pdev);
/**
* nvme_controller_status - This function checks the controller status
* @param ctrlr_regs
* @return SUCCESS or FAIL
*/
int nvme_controller_status(struct nvme_ctrl_reg __iomem *ctrlr_regs);
/**
* device_status_pci function returns the device status of
* the PCI Power Management status register set in PMCS register.
* @param device_data
* @return SUCCESS or FAIL
*/
int device_status_pmcs(u16 device_data);
/**
* device_status_msicap function returns the device status of
* Message signaled Interrupt status register in MC and MPEND
* @param pdev
* @param device_data
* @return SUCCESS or FAIL
*/
int device_status_msicap(struct pci_dev *pdev, u16 device_data);
/**
* device_status_msixcap function returns the device status of
* Message signaled Interrupt-X status register in MXC
* @param pdev
* @param device_data
* @return SUCCESS or FAIL
*/
int device_status_msixcap(struct pci_dev *pdev, u16 device_data);
/**
* device_status_pxcap function returns the device status of
* PCI express capability device status register in PXDS.
* @param pdev
* @param base_offset
* @return SUCCESS or FAIL
*/
int device_status_pxcap(struct pci_dev *pdev, u16 base_offset);
/**
* device_status_aercap function returns the device status of
* Advanced Error Reporting AER capability device status registers
* The register checked are AERUCES, AERCS and AERCC
* @param pdev
* @param base_offset
* @return SUCCESS or FAIL
*/
int device_status_aercap(struct pci_dev *pdev, u16 base_offset);
#endif