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Contador_A_7seg.syr
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Contador_A_7seg.syr
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Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.16 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.16 secs
--> Reading design: Contador_A_7seg.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "Contador_A_7seg.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "Contador_A_7seg"
Output Format : NGC
Target Device : xc3s200-5-ft256
---- Source Options
Top Module Name : Contador_A_7seg
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : Auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 8
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Users/daniel/Dropbox/Universidad/Semestre 7/Sis. digitales/laboratorio/jodido_guille/INV.vhd" in Library work.
Architecture behavioral of Entity inv is up to date.
Compiling vhdl file "C:/Users/daniel/Dropbox/Universidad/Semestre 7/Sis. digitales/laboratorio/jodido_guille/AND2.vhd" in Library work.
Architecture behavioral of Entity and2 is up to date.
Compiling vhdl file "C:/Users/daniel/Dropbox/Universidad/Semestre 7/Sis. digitales/laboratorio/jodido_guille/OR2.vhd" in Library work.
Architecture behavioral of Entity or2 is up to date.
Compiling vhdl file "C:/Users/daniel/Dropbox/Universidad/Semestre 7/Sis. digitales/laboratorio/jodido_guille/FFJK.vhd" in Library work.
Architecture behavioral of Entity ffjk is up to date.
Compiling vhdl file "C:/Users/daniel/Dropbox/Universidad/Semestre 7/Sis. digitales/laboratorio/jodido_guille/FFSR.vhd" in Library work.
Architecture behavioral of Entity ffsr is up to date.
Compiling vhdl file "C:/Users/daniel/Dropbox/Universidad/Semestre 7/Sis. digitales/laboratorio/jodido_guille/Contador_4b.vhd" in Library work.
Architecture behavioral of Entity contador_4b is up to date.
Compiling vhdl file "C:/Users/daniel/Dropbox/Universidad/Semestre 7/Sis. digitales/laboratorio/jodido_guille/AND3.vhd" in Library work.
Architecture behavioral of Entity and3 is up to date.
Compiling vhdl file "C:/Users/daniel/Dropbox/Universidad/Semestre 7/Sis. digitales/laboratorio/jodido_guille/Contador_8b.vhd" in Library work.
Entity <contador_8b> compiled.
Entity <contador_8b> (Architecture <structural>) compiled.
Compiling vhdl file "C:/Users/daniel/Dropbox/Universidad/Semestre 7/Sis. digitales/laboratorio/jodido_guille/Decodificador.vhd" in Library work.
Architecture dataflow of Entity decodificador is up to date.
Compiling vhdl file "C:/Users/daniel/Dropbox/Universidad/Semestre 7/Sis. digitales/laboratorio/jodido_guille/Contador_A_7seg.vhd" in Library work.
Entity <Contador_A_7seg> compiled.
Entity <Contador_A_7seg> (Architecture <Structural>) compiled.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <Contador_A_7seg> in library <work> (architecture <Structural>).
Analyzing hierarchy for entity <Contador_8b> in library <work> (architecture <structural>).
Analyzing hierarchy for entity <Decodificador> in library <work> (architecture <dataflow>).
Analyzing hierarchy for entity <AND2> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <INV> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <FFSR> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <Contador_4b> in library <work> (architecture <structural>).
Analyzing hierarchy for entity <AND3> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <OR2> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <INV> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <AND2> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <AND2> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <AND2> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <AND2> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <AND2> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <AND2> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <AND2> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <FFJK> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <AND2> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <AND2> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <AND2> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <AND2> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <AND2> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <AND2> in library <work> (architecture <behavioral>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <Contador_A_7seg> in library <work> (Architecture <Structural>).
Entity <Contador_A_7seg> analyzed. Unit <Contador_A_7seg> generated.
Analyzing Entity <Contador_8b> in library <work> (Architecture <structural>).
WARNING:Xst:819 - "C:/Users/daniel/Dropbox/Universidad/Semestre 7/Sis. digitales/laboratorio/jodido_guille/Contador_8b.vhd" line 169: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<A>
INFO:Xst:2679 - Register <Stopping_count> in unit <Contador_8b> has a constant value of 1 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <A> in unit <Contador_8b> has a constant value of 00101111 during circuit operation. The register is replaced by logic.
ERROR:Xst:827 - "C:/Users/daniel/Dropbox/Universidad/Semestre 7/Sis. digitales/laboratorio/jodido_guille/Contador_8b.vhd" line 169: Signal Start_LOAD cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.
-->
Total memory usage is 256336 kilobytes
Number of errors : 1 ( 0 filtered)
Number of warnings : 1 ( 0 filtered)
Number of infos : 2 ( 0 filtered)