From 315f6712605f60085b0f1ad9cfd321e35d7edbb5 Mon Sep 17 00:00:00 2001
From: Rodolfo Jordao <jordao@kth.se>
Date: Thu, 23 May 2024 17:59:10 +0200
Subject: [PATCH] Added a feasible version of tc3

---
 .../tc3_feasible.fiodl                        | 68 +++++++++++++++++++
 1 file changed, 68 insertions(+)
 create mode 100644 examples_and_benchmarks/novel/programmable_logic_area/tc3_feasible.fiodl

diff --git a/examples_and_benchmarks/novel/programmable_logic_area/tc3_feasible.fiodl b/examples_and_benchmarks/novel/programmable_logic_area/tc3_feasible.fiodl
new file mode 100644
index 00000000..62cc5635
--- /dev/null
+++ b/examples_and_benchmarks/novel/programmable_logic_area/tc3_feasible.fiodl
@@ -0,0 +1,68 @@
+systemgraph {
+  vertex "TC3"
+  [forsyde::io::lib::hierarchy::visualization::GreyBox, forsyde::io::lib::hierarchy::visualization::Visualizable]
+  (contained)
+  {}
+  vertex "Actor_1"
+  [forsyde::io::lib::hierarchy::behavior::BehaviourEntity, forsyde::io::lib::hierarchy::behavior::moc::MoCEntity, forsyde::io::lib::hierarchy::behavior::moc::sdf::SDFActor, forsyde::io::lib::hierarchy::implementation::functional::InstrumentedHardwareBehaviour, forsyde::io::lib::hierarchy::visualization::Visualizable]
+  (combFunctions, in_Actor_1, to_Actor_2)
+  {
+    "resourceRequirements": {
+      "FPGA": {
+        "Area": 10_l,
+        "Bram": 80000_l
+      }
+    },
+    "production": {
+      "to_Actor_2": 15_i
+    },
+    "latencyInSecsDenominators": {
+      "FPGA": 200000000_l
+    },
+    "latencyInSecsNumerators": {
+      "FPGA": 10_l
+    },
+    "consumption": {
+      "in_Actor_1": 5_i
+    },
+    "energyPerExecutionInJoules": {}
+  }
+  vertex "Actor_2"
+  [forsyde::io::lib::hierarchy::behavior::BehaviourEntity, forsyde::io::lib::hierarchy::behavior::moc::MoCEntity, forsyde::io::lib::hierarchy::behavior::moc::sdf::SDFActor, forsyde::io::lib::hierarchy::implementation::functional::InstrumentedHardwareBehaviour, forsyde::io::lib::hierarchy::visualization::Visualizable]
+  (combFunctions, from_Actor_1, out_Actor_2)
+  {
+    "resourceRequirements": {
+      "FPGA": {
+        "Area": 60000_l,
+        "Bram": 16000_l
+      }
+    },
+    "production": {
+      "out_Actor_2": 1_i
+    },
+    "latencyInSecsDenominators": {
+      "FPGA": 200000000_l
+    },
+    "latencyInSecsNumerators": {
+      "FPGA": 15_l
+    },
+    "consumption": {
+      "from_Actor_1": 3_i
+    },
+    "energyPerExecutionInJoules": {}
+  }
+  vertex "CH_Actor_1_Actor_2"
+  [forsyde::io::lib::hierarchy::behavior::moc::MoCEntity, forsyde::io::lib::hierarchy::behavior::moc::sdf::SDFChannel, forsyde::io::lib::hierarchy::implementation::functional::BufferLike, forsyde::io::lib::hierarchy::visualization::Visualizable]
+  (consumer, from_Actor_1, producer, to_Actor_2, tokenDataType)
+  {
+    "elementSizeInBits": 8_l,
+    "numInitialTokens": 0_i
+  }
+  edge [forsyde::io::lib::hierarchy::visualization::VisualContainment] from "TC3" port "contained" to "Actor_1" 
+  edge [forsyde::io::lib::hierarchy::visualization::VisualContainment] from "TC3" port "contained" to "Actor_2" 
+  edge [forsyde::io::lib::hierarchy::visualization::VisualContainment] from "TC3" port "contained" to "CH_Actor_1_Actor_2" 
+  edge [forsyde::io::lib::hierarchy::behavior::moc::sdf::SDFNetworkEdge] from "Actor_1" to "CH_Actor_1_Actor_2" port "producer"
+  edge [forsyde::io::lib::hierarchy::behavior::moc::sdf::SDFNetworkEdge] from "CH_Actor_1_Actor_2" port "consumer" to "Actor_2" 
+  edge [forsyde::io::lib::hierarchy::behavior::moc::sdf::SDFNetworkEdge,forsyde::io::lib::hierarchy::visualization::VisualConnection] from "Actor_1" port "to_Actor_2" to "CH_Actor_1_Actor_2" 
+  edge [forsyde::io::lib::hierarchy::behavior::moc::sdf::SDFNetworkEdge,forsyde::io::lib::hierarchy::visualization::VisualConnection] from "CH_Actor_1_Actor_2" port "to_Actor_2" to "Actor_2" port "from_Actor_1"
+}
\ No newline at end of file