When you run make gpio_defaults on a caravel_user_project, it parses the contents of verilog/rtl/user_defines.v and we've noticed an issue where Verilog block comments are parsed incorrectly and treated as real code.

The following code should result in mag/gpio_defaults_block_1111.mag being created, but instead it uses the value in the comments and so creates mag/gpio_defaults_block_1eee.mag:

`define USER_CONFIG_GPIO_37_INIT 13'h1111
/*
`define USER_CONFIG_GPIO_37_INIT 13'h1eee
*/

...and thus it looks like the latter (unintended, commented) value gets used in synthesis.

I think this came to light because of @d-m-bailey running a check per #532